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Commenced in January 2007 Frequency: Monthly Edition: International Publications Count: 29526

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A Study on ESD Protection Circuit Applying Silicon Controlled Rectifier-Based Stack Technology with High Holding Voltage
In this study, an improved Electrostatic Discharge (ESD) protection circuit with low trigger voltage and high holding voltage is proposed. ESD has become a serious problem in the semiconductor process because the semiconductor density has become very high these days. Therefore, much research has been done to prevent ESD. The proposed circuit is a stacked structure of the new unit structure combined by the Zener Triggering (SCR ZTSCR) and the High Holding Voltage SCR (HHVSCR). The simulation results show that the proposed circuit has low trigger voltage and high holding voltage. And the stack technology is applied to adjust the various operating voltage. As the results, the holding voltage is 7.7 V for 2-stack and 10.7 V for 3-stack.
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[1] Albert Z, H. Wang, On-Chip ESD Protection for Integrated devices 2nd ed. Springer, US, 2002.
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[8] J. Y. Lee "Analysis of SCR, MVSCR, LVTSCR With I-V Characteristic and Turn-On-Time," j.inst.Korean.electr.electron.eng, vol. 20, no. 3, pp. 295-398, 2016.
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[12] Y. Koo, K. Lee, K. Kim, and J. Kwon, “Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology,” Microelectronics Journal, vol. 40, pp. 1007-1012, 2009.
[13] S.-L. Jang, L.-S. Lin, and S.-H. Li, “Temperature-dependent dynamic trig-gering characteristics of SCR-type ESD protection circuits,” Solid-State Electronics, vol. 45, pp. 2005-2009, 2001.
[14] V. A. Vashchenko, A. Concannon, M. ter Beek, and P. Hopper "High Holding Voltage Cascoded LVTSCR Structures for 5.5-V Tolerant ESD Protection Clamps," IEEE Transactions on Device and Materials Reliability, vol. 4, no. 2, pp. 273-280, 2004.
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