In this paper we present high performance
dynamically allocated multi-queue (DAMQ) buffer schemes for fault
tolerance systems on chip applications that require an interconnection
network. Two virtual channels shared the same buffer space. Fault
tolerant mechanisms for interconnection networks are becoming a
critical design issue for large massively parallel computers. It is also
important to high performance SoCs as the system complexity keeps
increasing rapidly. On the message switching layer, we make
improvement to boost system performance when there are faults
involved in the components communication. The proposed scheme is
when a node or a physical channel is deemed as faulty, the previous
hop node will terminate the buffer occupancy of messages destined
to the failed link. The buffer usage decisions are made at switching
layer without interactions with higher abstract layer, thus buffer
space will be released to messages destined to other healthy nodes
quickly. Therefore, the buffer space will be efficiently used in case
fault occurs at some nodes.
 C.J. Glass and L.M. Ni, "The Turn Model for Adaptive Routing",
Proceedings of the 19th Annual International Symposium on Computer
Architecture, May 1992. pp: 278-287.
 C.J. Glass and L.M. Ni, "Adaptive Routing in Mesh-connected
Networks", Proceedings of the 12th International Conference on
Distributed Computing Systems, June 1992. pp: 12-19.
 Ge-Ming Chiu, "The odd-even turn model for adaptive routing", IEEE
Transactions on Parallel and Distributed Systems, Volume 11, Issue 7,
July 2000. pp: 729 - 738.
 P. P. Pande, C. Grecu, M. Jones, A. Ivanov, R. Saleh, "Performance
Evaluation and Design Trade-offs for Network on Chip Interconnect
Architectures", IEEE Transactions on Computers, vol. 54, no. 8, August
2005. pp; 1025-1040.
 Ge-Ming Chiu, "The Odd-even Turn Model for Adaptive Routing",
IEEE Transactions on Parallel and Distributed Systems, Volume 11,
Issue 7, July 2000. pp. 729 - 738.
 Jie Wu, "A Fault-tolerant and Deadlock-free Routing Protocol in 2D
Meshes Based on Odd-even Turn Model", IEEE Transactions on
Computers, Volume 52, Issue 9, Sept. 2003. pp. 1154 - 1169.
 Jie Wu, Dajin Wang, "Fault-tolerant and Deadlock-free Routing in 2-D
Meshes Using Rectilinear-monotone Polygonal Fault Blocks",
International Conference on Parallel Processing, 18-21 Aug. 2002. pp.
247 - 254.
 Y. Tamir and G. L. Frazier, "Dynamically-allocated multiqueue buffers
for VLSI communication switches," IEEE Transactions on Computers,
vol. 41, no. 2, June 1992, 725-737.
 R. Sivaram, C. B. Stunkel, and D. K. Panda, "HIPIQS: A High
Performance switch architecture using input queueing," IPPS/SPDP -98,
Orlando, FL, March 1998, 134-143.
 J. Park, B. O-Krafka, S. Vassiliadis, and J. Delgado-Frias, "Design and
evaluation of a DAMQ multiprocessor network with self-compacting
buffers," IEEE Supercomputing -94, Conference on High Performance
Computing and Communications, Nov. 14-18, 1994, 713-722.
 J. Liu, J. G. Delgado-Frias, "A Shared Self-Compacting Buffer for
Network-On-Chip Systems," 49th IEEE Int. Midwest Symposium on
Circuits and Systems. August 2006.