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Commenced in January 2007 Frequency: Monthly Edition: International Publications Count: 29526


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9997712
Design and Analysis of a Low Power High Speed 1 Bit Full Adder Cell Based On TSPC Logic with Multi-Threshold CMOS
Authors:
Abstract:
An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high threshold voltage sleep transistor is used to reduce the static power dissipation in standby mode. The circuit is designed and simulated in TSPICE using TSMC 180nm CMOS process. Average power consumption, delay and power-delay product is measured which showed considerable improvement in performance over the existing full adder designs.
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References:

[1] Yi WEI and Ji-zhong SHEN, "Design of a novel low power 8 transistor full adder cell, Journal of Zhejiang University-SCIENCE C (Computers & Electronics),ISSN 1869-1951 (Print); ISSN 1869-196X (Online), pp. 604-607.
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