Design and Analysis of a Low Power High Speed 1 Bit Full Adder Cell Based On TSPC Logic with Multi-Threshold CMOS
 Yi WEI and Ji-zhong SHEN, "Design of a novel low power 8 transistor full adder cell, Journal of Zhejiang University-SCIENCE C (Computers & Electronics),ISSN 1869-1951 (Print); ISSN 1869-196X (Online), pp. 604-607.
 M. Anis, S. Areibi and M. Elmasry, "Design and Optimization of Multi-Threshold CMOS(MTCMOS) circuits”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems,22(10), pp. 1324-1342, October 2003.
 Shubhajit Roy Chowdhury, Aritra Banerjee, Aniruddha Roy, HiranmaySaha, " A high speed 8 transistor full adder design using novel 3 transistor XOR Gates”, International Journal of Electrical and Computer Engineering, 2008, pp. 784-790
 Volker Schindler, "A low power True Single Phase Clock(TSPC) Full-Adder”, IEEE Proceedings of the 22nd European Solid-State Circuits Conference,1996.
 Jiren Yuan and ChristerSvensson, "High-Speed CMOS Circuit Technique”, IEEE Journal of Solid-State Circuits, Vol. 24, No. 1, February, 1989, pp. 62-70.
 Reto Zimmermann and Wolfgang Fichtner, "Low Power Logic Styles: CMOS versus Pass-Transistor Logic”, IEEE Journal of Solid-State Circuits, Vol. 32, No. 7, July 1997.
 Dake Liu and ChristerSvensson, "Trading Speed for Low Power by Choice of Supply and Threshold Voltages”, IEEE Journal of Solid-State Circuits, Vol. 28, No. 1, January 1993.
 Abdoul M. Rjoub and Al-Mamoon Al-Othman, "The Influence of the Nanometer Technology on the Performance of CPL Full Adders”, Journal of Computers, Vol. 5, No. 3, March 2010.
 AnanthaP.Chandrakasan, Samuel Sheng and Robert W. Broadersen, "Low Power CMOS Digital Design”, IEEE Journal of Solid-State Circuits, Vol. 27, No. 4, April 1992.
 M. Anis, S. Areibi and M. Elmasry, "Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique”, Proceedings of 39th Design Automation Conference, 2002, pp. 480-485.