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9998119
Design and Analysis of an 8T Read Decoupled Dual Port SRAM Cell for Low Power High Speed Applications
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Abstract:
Speed, power consumption and area, are some of the most important factors of concern in modern day memory design. As we move towards Deep Sub-Micron Technologies, the problems of leakage current, noise and cell stability due to physical parameter variation becomes more pronounced. In this paper we have designed an 8T Read Decoupled Dual Port SRAM Cell with Dual Threshold Voltage and characterized it in terms of read and write delay, read and write noise margins, Data Retention Voltage and Leakage Current. Read Decoupling improves the Read Noise Margin and static power dissipation is reduced by using Dual-Vt transistors. The results obtained are compared with existing 6T, 8T, 9T SRAM Cells, which shows the superiority of the proposed design. The Cell is designed and simulated in TSPICE using 90nm CMOS process.
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References:

[1] ParidhiAthe, S. Dasgupta, "A Comparative Study of 6T, 8T and 9T Decanano SRAM Cell”, IEEE Symposium on Industrial Electronics and Applications, 2009, pp. 889-894.
[2] BehnamAmelifard, FarzanFallah, MassoudPedram, "Low-leakage SRAM Design with Dual VtTransistors”, ISQUED ’06 Proceedings of the 7th International Symposium on Quality Electronic Design, pp. 729-734.
[3] ArunRamnathRamani and Ken Choi, "A Novel 9T SRAM Design in Sub-Threshold Region”, IEEE International Conference on Electro/Information Technology (EIT), 2011, pp. 1-6.
[4] Debasis Mukherjee, Hemanta Kr. Mondal and B.V.R Reddy, "Static Noise Margin Analysis of SRAM Cell for High Speed Application, International Journal of Computer Science Issues, Vol. 7 Issue 5, September 2010, ISSN: 1694-0814, pp. 175-180.
[5] Hiroki Noguchi, Shunsuke Okumura, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi and Masahiko Yoshimoto, " Which is the Best Dual-Port SRAM in 45-nm Process Technology? – 8T, 10T Single-Ended, and 10T Differential”, IEEE International Conference on Integrated circuit Design and Technology and Tutorial, 2008, pp. 55-58.
[6] Jawar Singh, Dhiraj K. Pradhan, Simon Hollis, Saraju P. Mohantyand J. Mathew, "Single-Ended 6T SRAM with Isolated Read-Port for Low Power Embedded Systems”, Conference and Exhibition on Design, Automation and Test, Europe, 2009, pp. 917-922.
[7] Koichi Takeda, Yasuhiko Hagihara, Yoshiharu Aimoto, Masahiro Nomura, YoetsuNakazawa, Toshio Ishiiand Hiroyuki Kobatake, " A Read-Static-Noise-Margin-Free SRAM Cell for Low-VDD and High-Speed Applications”, IEEE Journal of Solid-state Circuits, Vol. 41, No. 1, January 2006, pp. 113-121.
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