Dynamic Power Reduction in Sequential Circuits Using Look Ahead Clock Gating Technique
 Qing Wu, Massoud Pedram and Xunwei Wu. “Clock-Gating and its
Application to Low Power Design of Sequential Circuits”, IEEE
Transactions on Circuits And Systems—I: Fundamental Theory And
Applications, Vol. 47, No. 103, March 2000.
 V.G. Oklobdzija, “Digital System Clocking, High-Performance and
Low-Power Aspects”, New York, NY, USA: Wiley, 2003.
 Shmuel Wimer and Israel Koren, “Design Flow for Flip-Flop Grouping
in Data-Driven Clock Gating”, IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, Vol. 22, No. 4, pp. 771-778, April 2014.
 Shmuel Wimer and Arye Albahari, “A Look-Ahead Clock Gating Based
On Auto–Gated Flip-Flops”, IEEE Transactions on Circuits and
Systems-I: Regular Papers, Vol. 61, No. 5, pp. 1465-1472, May 2014.
 L.Benini, A. Bogliolo, and G. De Micheli, “A survey on design
techniques for system-level dynamic power management”, IEEE
Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8,
No. 3, pp. 299–316, June 2000.
 Walter Aloisi and Rosario Mita, “Gated-Clock Design of Linear-
Feedback Shift Register”, IEEE Transactions on Circuits and
Systems—II: Express Briefs, Vol. 55, No. 6, pp. 546-550, June 2008.
 M. Lowy, “Parallel implementation of linear feedback shift register for
low power applications,” IEEE Transactions on Circuits and Systems-
II, Analog and Digital Signal Process, Vol. 43, No. 6, June 1996.
 Neil H.E.Weste, David Harris and Ayan Banerjee, “CMOS VLSI
Design – A circuits and systens perspective”, Pearson Addison Wesley,
 Solomon W.Golomb and Pey-Feng Lee, “Irreducible Polynomials
Which Divide Trinomials Over GF (2)”, IEEE Transactions on
Information Theory, Vol. 53, No. 2, February 2007.
 Shmuel Wimer and Israel Koren, “The Optimal Fan-Out of Clock
Network for Power Reduction by Adaptive Gating”, IEEE Transactions
on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 10,
 Shmuel Wimer, Israel Koren and Itamar cohen, “Adaptive Clock Gating
for Shift Register base Circuits”, IEEE 26-th Convention of Electrical
and Electronics Engineers in Israel,2010.
 Li Li, Ken choi, Seongmo Park and Mookyung Chung, “Selective Clock
Gating by using Wasting Toggle Rate”, IEEE 2009.
 Cadence Tutorial, “Power Analysis using CADENCE Encounter”,