Open Science Research Excellence

Open Science Index

Commenced in January 2007 Frequency: Monthly Edition: International Publications Count: 29396

Select areas to restrict search in scientific publication database:
Dynamic Power Reduction in Sequential Circuits Using Look Ahead Clock Gating Technique
In this paper, a novel Linear Feedback Shift Register (LFSR) with Look Ahead Clock Gating (LACG) technique is presented to reduce the power consumption in modern processors and System-on-Chip. Clock gating is a predominant technique used to reduce unwanted switching of clock signals. Several clock gating techniques to reduce the dynamic power have been developed, of which LACG is predominant. LACG computes the clock enabling signals of each flip-flop (FF) one cycle ahead of time, based on the present cycle data of the flip-flops on which it depends. It overcomes the timing problems in the existing clock gating methods like datadriven clock gating and Auto-Gated flip-flops (AGFF) by allotting a full clock cycle for the determination of the clock enabling signals. Further to reduce the power consumption in LACG technique, FFs can be grouped so that they share a common clock enabling signal. Simulation results show that the novel grouped LFSR with LACG achieves 15.03% power savings than conventional LFSR with LACG and 44.87% than data-driven clock gating.
Digital Object Identifier (DOI):


[1] Qing Wu, Massoud Pedram and Xunwei Wu. “Clock-Gating and its Application to Low Power Design of Sequential Circuits”, IEEE Transactions on Circuits And Systems—I: Fundamental Theory And Applications, Vol. 47, No. 103, March 2000.
[2] V.G. Oklobdzija, “Digital System Clocking, High-Performance and Low-Power Aspects”, New York, NY, USA: Wiley, 2003.
[3] Shmuel Wimer and Israel Koren, “Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 4, pp. 771-778, April 2014.
[4] Shmuel Wimer and Arye Albahari, “A Look-Ahead Clock Gating Based On Auto–Gated Flip-Flops”, IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol. 61, No. 5, pp. 1465-1472, May 2014.
[5] L.Benini, A. Bogliolo, and G. De Micheli, “A survey on design techniques for system-level dynamic power management”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8, No. 3, pp. 299–316, June 2000.
[6] Walter Aloisi and Rosario Mita, “Gated-Clock Design of Linear- Feedback Shift Register”, IEEE Transactions on Circuits and Systems—II: Express Briefs, Vol. 55, No. 6, pp. 546-550, June 2008.
[7] M. Lowy, “Parallel implementation of linear feedback shift register for low power applications,” IEEE Transactions on Circuits and Systems- II, Analog and Digital Signal Process, Vol. 43, No. 6, June 1996.
[8] Neil H.E.Weste, David Harris and Ayan Banerjee, “CMOS VLSI Design – A circuits and systens perspective”, Pearson Addison Wesley, 2005.
[9] Solomon W.Golomb and Pey-Feng Lee, “Irreducible Polynomials Which Divide Trinomials Over GF (2)”, IEEE Transactions on Information Theory, Vol. 53, No. 2, February 2007.
[10] Shmuel Wimer and Israel Koren, “The Optimal Fan-Out of Clock Network for Power Reduction by Adaptive Gating”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 10, October 2012.
[11] Shmuel Wimer, Israel Koren and Itamar cohen, “Adaptive Clock Gating for Shift Register base Circuits”, IEEE 26-th Convention of Electrical and Electronics Engineers in Israel,2010.
[12] Li Li, Ken choi, Seongmo Park and Mookyung Chung, “Selective Clock Gating by using Wasting Toggle Rate”, IEEE 2009.
[13] Cadence Tutorial, “Power Analysis using CADENCE Encounter”, Sep.2008.
Vol:13 No:03 2019Vol:13 No:02 2019Vol:13 No:01 2019
Vol:12 No:12 2018Vol:12 No:11 2018Vol:12 No:10 2018Vol:12 No:09 2018Vol:12 No:08 2018Vol:12 No:07 2018Vol:12 No:06 2018Vol:12 No:05 2018Vol:12 No:04 2018Vol:12 No:03 2018Vol:12 No:02 2018Vol:12 No:01 2018
Vol:11 No:12 2017Vol:11 No:11 2017Vol:11 No:10 2017Vol:11 No:09 2017Vol:11 No:08 2017Vol:11 No:07 2017Vol:11 No:06 2017Vol:11 No:05 2017Vol:11 No:04 2017Vol:11 No:03 2017Vol:11 No:02 2017Vol:11 No:01 2017
Vol:10 No:12 2016Vol:10 No:11 2016Vol:10 No:10 2016Vol:10 No:09 2016Vol:10 No:08 2016Vol:10 No:07 2016Vol:10 No:06 2016Vol:10 No:05 2016Vol:10 No:04 2016Vol:10 No:03 2016Vol:10 No:02 2016Vol:10 No:01 2016
Vol:9 No:12 2015Vol:9 No:11 2015Vol:9 No:10 2015Vol:9 No:09 2015Vol:9 No:08 2015Vol:9 No:07 2015Vol:9 No:06 2015Vol:9 No:05 2015Vol:9 No:04 2015Vol:9 No:03 2015Vol:9 No:02 2015Vol:9 No:01 2015
Vol:8 No:12 2014Vol:8 No:11 2014Vol:8 No:10 2014Vol:8 No:09 2014Vol:8 No:08 2014Vol:8 No:07 2014Vol:8 No:06 2014Vol:8 No:05 2014Vol:8 No:04 2014Vol:8 No:03 2014Vol:8 No:02 2014Vol:8 No:01 2014
Vol:7 No:12 2013Vol:7 No:11 2013Vol:7 No:10 2013Vol:7 No:09 2013Vol:7 No:08 2013Vol:7 No:07 2013Vol:7 No:06 2013Vol:7 No:05 2013Vol:7 No:04 2013Vol:7 No:03 2013Vol:7 No:02 2013Vol:7 No:01 2013
Vol:6 No:12 2012Vol:6 No:11 2012Vol:6 No:10 2012Vol:6 No:09 2012Vol:6 No:08 2012Vol:6 No:07 2012Vol:6 No:06 2012Vol:6 No:05 2012Vol:6 No:04 2012Vol:6 No:03 2012Vol:6 No:02 2012Vol:6 No:01 2012
Vol:5 No:12 2011Vol:5 No:11 2011Vol:5 No:10 2011Vol:5 No:09 2011Vol:5 No:08 2011Vol:5 No:07 2011Vol:5 No:06 2011Vol:5 No:05 2011Vol:5 No:04 2011Vol:5 No:03 2011Vol:5 No:02 2011Vol:5 No:01 2011
Vol:4 No:12 2010Vol:4 No:11 2010Vol:4 No:10 2010Vol:4 No:09 2010Vol:4 No:08 2010Vol:4 No:07 2010Vol:4 No:06 2010Vol:4 No:05 2010Vol:4 No:04 2010Vol:4 No:03 2010Vol:4 No:02 2010Vol:4 No:01 2010
Vol:3 No:12 2009Vol:3 No:11 2009Vol:3 No:10 2009Vol:3 No:09 2009Vol:3 No:08 2009Vol:3 No:07 2009Vol:3 No:06 2009Vol:3 No:05 2009Vol:3 No:04 2009Vol:3 No:03 2009Vol:3 No:02 2009Vol:3 No:01 2009
Vol:2 No:12 2008Vol:2 No:11 2008Vol:2 No:10 2008Vol:2 No:09 2008Vol:2 No:08 2008Vol:2 No:07 2008Vol:2 No:06 2008Vol:2 No:05 2008Vol:2 No:04 2008Vol:2 No:03 2008Vol:2 No:02 2008Vol:2 No:01 2008
Vol:1 No:12 2007Vol:1 No:11 2007Vol:1 No:10 2007Vol:1 No:09 2007Vol:1 No:08 2007Vol:1 No:07 2007Vol:1 No:06 2007Vol:1 No:05 2007Vol:1 No:04 2007Vol:1 No:03 2007Vol:1 No:02 2007Vol:1 No:01 2007