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Commenced in January 2007 Frequency: Monthly Edition: International Publications Count: 29526

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FPGA-based Systems for Evolvable Hardware
Since 1992, year where Hugo de Garis has published the first paper on Evolvable Hardware (EHW), a period of intense creativity has followed. It has been actively researched, developed and applied to various problems. Different approaches have been proposed that created three main classifications: extrinsic, mixtrinsic and intrinsic EHW. Each of these solutions has a real interest. Nevertheless, although the extrinsic evolution generates some excellent results, the intrinsic systems are not so advanced. This paper suggests 3 possible solutions to implement the run-time configuration intrinsic EHW system: FPGA-based Run-Time Configuration system, JBits-based Run-Time Configuration system and Multi-board functional-level Run-Time Configuration system. The main characteristic of the proposed architectures is that they are implemented on Field Programmable Gate Array. A comparison of proposed solutions demonstrates that multi-board functional-level run-time configuration is superior in terms of scalability, flexibility and the implementation easiness.
Digital Object Identifier (DOI):


[1] H. de Garis. "Evolvable Hardware: Principles and Practice". Communications of the Association for Computer Machinery (CACM Journal). August 1997.
[2] X. Yao, T. Higuchi. "Promises and challenges of evolvable hardware" IEEE Trans. Systems, Man and Cybernetics, Part C, vol. 29, Pages. 87 - 97, February 1999.
[3] D. E. Goldberg. Genetic algorithm in search, optimization and machine learning. Addison-Wesley Publishing Company, Incorporated, Reading, Massachusetts, 1989.
[4] N. J. Macias. "The PIG paradigm: the design and use of a massively parallel fine grained self-reconfigurable infinitely scalable architecture". Proceedings of the First NASA/DoD Workshop on, 19-21. pp: 175-180. 1999.
[5] A. Stoica, D. Keymeulen, D. Vu, R. Zebulum, I. Ferguson, T. Daud, T. Arsian, G. Xin. "Evolutionary recovery of electronic circuits from radiation induced faults". Evolutionary Computation, 2004. CEC2004. Congress on, Volume: 2, 19-23. pp: 1786-1793. Vol.2. 2004.
[6] J. Langeheine, K. Meier, J. Schemmel, M. Trefzer. "Intrinsic evolution of digital-to-analog converters using a CMOS FPTA chip". Evolvable Hardware, 2004. Proceedings. 2004 NASA/DoD Conference on, 24-26. pp: 18-25. 2004.
[7] I. Kajitani, et al. "A gate-level EHW chip: Implementing GA operations and reconfigurable hardware on a single LSI". (Proc. of Second International Conference on Evolvable Systems: From Biology to Hardware (ICES1998)). Springer Verlag. pp. 1-12.
[8] V. Baumgarte, F. May, A N├╝ckel, M. Vorbach, and M. Weinhardt. "PACT XPP - A self-Reconfigurable Data Processing Architecture". Presented at ERSA'01, Las Vegas, NV, (c) CSREA Press. 2001.
[9] A. Thompson. "Exploring Beyond the Scope of Human Design: Automatic generation of FPGA configurations through artificial evolution." 8th Annual Advanced PLD & FPGA Conference 1998.
[10] L. Sekanina, S. Friedl. "On Routine Implementation of Virtual Evolvable Devices Using COMBO6". In: Proc. of the 2004 NASA/DoD Conference on Evolvable Hardware, Los Alamitos, US, ICSP. pp. 63-70, ISBN 0-7695-2145-2. 2004.
[11] M. Iwata, I. Kajitani, Y. Liu, N. Kajihara, T. Higuchi. "Implementation of a Gate-Level Evolvable Hardware Chip." Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science 2210 (Proc. of ICES2001). Springer Verlag. pp. 38-49. 2001.
[12] G. Tufte, P. C. Haddow. "Identification of functionality during development on a virtual Sblock FPGA". Evolutionary Computation, 2003. CEC '03. The 2003 Congress on. Volume: 1. pp. 8-12. Dec. 2003.
[13] I. Rechenberg, "Evolution Strategy", in J. Zurada, R. Marks II, and C. Robinson (Eds.), Computational Intelligence: Imitating Life, 1994, pp. 147-159.
[14] J. Torresen, J. W. Bakke and L. Sekanina. "Recognizing Speed Limit Sign Numbers by Evolvable Hardware." In proc. of 8th International Conference on Parallel Problem Solving from Nature (PPSN VIII). UK. 2004.
[15] Xilinx. "Virtex-E 1.8V FPGA Complete Data Sheet". 14/3/2003.
[16] Xilinx. "Spartan-II 2.5V FPGA Complete Data Sheet". 9/3/2003.
[17] T. Kalganova, J.F. Miller. "Evolving more efficient digital circuits by allowing circuit layout evolution and multi-objective fitness". Proc. of the First NASA/DoD Workshop on Evolvable Hardware pp. 54-65.
[18] Xilinx. "XAPP151 - Virtex Series Configuration Architecture User Guide", v1.6. 24/3/2003.
[19] W. Huang, S. Mitra, E. J. McCluskey, "Fast Run-Time Fault Location in Dependable FPGA-Based Applications", DFT 2001.
[20] Xilinx. "Virtex-II Platform FPGA User Guide", v1.9. pp. 206-214. 05/8/2004.
[21] L. Sekanina, "Towards Evolvable IP Cores for FPGAs". In: Proc. of The 2003 NASA/DoD Conference on Evolvable Hardware, Los Alamitos, US, ICSP, pp. 145-154, ISBN 0-7695-1977-6. 2003.
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