Open Science Research Excellence

Open Science Index

Commenced in January 2007 Frequency: Monthly Edition: International Publications Count: 29830

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Interplay of Power Management at Core and Server Level
While the feature sizes of recent Complementary Metal Oxid Semiconductor (CMOS) devices decrease the influence of static power prevails their energy consumption. Thus, power savings that benefit from Dynamic Frequency and Voltage Scaling (DVFS) are diminishing and temporal shutdown of cores or other microchip components become more worthwhile. A consequence of powering off unused parts of a chip is that the relative difference between idle and fully loaded power consumption is increased. That means, future chips and whole server systems gain more power saving potential through power-aware load balancing, whereas in former times this power saving approach had only limited effect, and thus, was not widely adopted. While powering off complete servers was used to save energy, it will be superfluous in many cases when cores can be powered down. An important advantage that comes with that is a largely reduced time to respond to increased computational demand. We include the above developments in a server power model and quantify the advantage. Our conclusion is that strategies from datacenters when to power off server systems might be used in the future on core level, while load balancing mechanisms previously used at core level might be used in the future at server level.
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[1] M. B. Taylor. A Landscape of the New Dark Silicon Design Regime. IEEE Micro, 33(5):8–19, 2013.
[2] R. Sch¨one, D. Molka, and M. Werner. Wake-up latencies for processor idle states on current x86 processors. Computer Science - Research and Development, pages 1–9, 2014.
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[8] A. Dhingra and S. Paul. A Survey of Energy Efficient Data Centres in a Cloud Computing Environment. IJARCCE, 2(10):4033–4040, 2013.
[9] J. Leverich, M. Monchiero, V. Talwar, P. Ranganathan, and C. Kozyrakis. Power Management of Datacenter Workloads Using Per-Core Power Gating. IEEE Computer Architecture Letters, 8(2):48–51, February 2009.
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[11] G. Da Costa. Heterogeneity: The Key to Achieve Power-Proportional Computing. 13th Symp. on Cluster, Cloud, and Grid Computing, pages 656–662, May 2013.
[12] R. H. Dennard, F. H. Gaensslen, Y. Hwa-Nien, V.L. Rideout, E. Bassous, and A. LeBlanc. Design of Ion-Implanted MOSFETs with Very Small Physical Dimensions. Proc. of Solid-State Circuits, 9(5):256–268, 1974.
[13] H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam, and D. Burger. Power Limitations and Dark Silicon Challenge the Future of Multicore. ACM Transactions on Computer Systems, 30(3):1–27, 2012.
[14] N. Hardavellas, M. Ferdman, B. Falsafi, and A. Ailamaki. Toward dark silicon in servers. IEEE Micro, 31(4):6–15, 2011.
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[16] M. B. Taylor. Is dark silicon useful? Harnessing the four horsemen of the coming dark silicon apocalypse. In Proc. of Design Automation Conference, pages 1131–1136. ACM, 2012.
[17] G. Venkatesh, J. Sampson, N. Goulding, S. Garcia, V. Bryksin, J. Lugo-Martinez, S. Swanson, and M. B. Taylor. Conservation cores: Reducing the energy of mature computations. In Int. Conf. on Architectural Support for Programming Languages and Operating Systems, pages 205–218. ACM, 2010.
[18] A. Carroll and G. Heiser. Mobile Multicores : Use Them or Waste Them. ACM SIGOPS Oper. Syst. Rev., 48(1):44–48, 2014.
[19] N. Madan, A. Buyuktosunoglu, P. Bose, and M. Annavaram. A case for guarded power gating for multi-core processors. 17th Int. Symp. on HPC Architecture, pages 291–300, 2011.
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