Optimizing the Number of Bits/Stage in 10-Bit, 50Ms/Sec Pipelined A/D Converter Considering Area, Speed, Power and Linearity
Pipeline ADCs are becoming popular at high speeds
and with high resolution. This paper discusses the options of number
of bits/stage conversion techniques in pipelined ADCs and their
effect on Area, Speed, Power Dissipation and Linearity. The basic
building blocks like op-amp, Sample and Hold Circuit, sub converter,
DAC, Residue Amplifier used in every stage is assumed to be
identical. The sub converters use flash architectures. The design is
implemented using 0.18
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