The Simulation based VLSI Implementation of

\r\nFELICS (Fast Efficient Lossless Image Compression System)

\r\nAlgorithm is proposed to provide the lossless image compression and

\r\nis implemented in simulation oriented VLSI (Very Large Scale

\r\nIntegrated). To analysis the performance of Lossless image

\r\ncompression and to reduce the image without losing image quality

\r\nand then implemented in VLSI based FELICS algorithm. In FELICS

\r\nalgorithm, which consists of simplified adjusted binary code for

\r\nImage compression and these compression image is converted in

\r\npixel and then implemented in VLSI domain. This parameter is used

\r\nto achieve high processing speed and minimize the area and power.

\r\nThe simplified adjusted binary code reduces the number of arithmetic

\r\noperation and achieved high processing speed. The color difference

\r\npreprocessing is also proposed to improve coding efficiency with

\r\nsimple arithmetic operation. Although VLSI based FELICS

\r\nAlgorithm provides effective solution for hardware architecture

\r\ndesign for regular pipelining data flow parallelism with four stages.

\r\nWith two level parallelisms, consecutive pixels can be classified into

\r\neven and odd samples and the individual hardware engine is

\r\ndedicated for each one. This method can be further enhanced by

\r\nmultilevel parallelisms.<\/p>\r\n",
"references": null,
"publisher": "World Academy of Science, Engineering and Technology",
"index": "International Science Index 93, 2014"
}