Open Science Research Excellence
Sunil Jadav and  Rajeevan Chandel Munish Vashishath,  A Superior Delay Estimation Model for VLSI Interconnect in Current Mode Signaling.   journal   = {International Journal of Computer, Electrical, Automation, Control and Information Engineering}, [online]. World Academy of Science, Engineering and Technology. February 2015, vol. 98(2). 492 - 497[viewed 24 May 2019]. Available from: http://waset.org/publications/10001108.