Today’s VLSI networks demands for high speed. And

\r\nin this work the compact form mathematical model for current mode

\r\nsignalling in VLSI interconnects is presented.RLC interconnect line

\r\nis modelled using characteristic impedance of transmission line and

\r\ninductive effect. The on-chip inductance effect is dominant at lower

\r\ntechnology node is emulated into an equivalent resistance. First order

\r\ntransfer function is designed using finite difference equation, Laplace

\r\ntransform and by applying the boundary conditions at the source and

\r\nload termination. It has been observed that the dominant pole

\r\ndetermines system response and delay in the proposed model. The

\r\nnovel proposed current mode model shows superior performance as

\r\ncompared to voltage mode signalling. Analysis shows that current

\r\nmode signalling in VLSI interconnects provides 2.8 times better

\r\ndelay performance than voltage mode. Secondly the damping factor

\r\nof a lumped RLC circuit is shown to be a useful figure of merit.<\/p>\r\n",
"references": null,
"publisher": "World Academy of Science, Engineering and Technology",
"index": "International Science Index 98, 2015"
}