Open Science Research Excellence
%0 Journal Article
%A R. Abdul Wahab and  R. Mohd Fuad Tengku Aziz and  N. Othman and  S. Saleh and  N. Razali and  M. Al Baqir Zinal Abidin and  M. Hanif Md Nasir
%D 2015 
%J  International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering
%B World Academy of Science, Engineering and Technology
%I International Science Index 106, 2015
%T Physical Verification Flow on Multiple Foundries
%U http://waset.org/publications/10002417
%V 106
%X This paper will discuss how we optimize our physical
verification flow in our IC Design Department having various rule
decks from multiple foundries. Our ultimate goal is to achieve faster
time to tape-out and avoid schedule delay. Currently the physical
verification runtimes and memory usage have drastically increased
with the increasing number of design rules, design complexity, and
the size of the chips to be verified. To manage design violations, we
use a number of solutions to reduce the amount of violations needed
to be checked by physical verification engineers. The most important
functions in physical verifications are DRC (design rule check), LVS
(layout vs. schematic), and XRC (extraction). Since we have a
multiple number of foundries for our design tape-outs, we need a
flow that improve the overall turnaround time and ease of use of the
physical verification process. The demand for fast turnaround time is
even more critical since the physical design is the last stage before
sending the layout to the foundries.
%P 1101 - 1104