Open Science Research Excellence
%0 Journal Article
%A Vishal Awasthi and  Krishna Raj
%D 2016 
%J  International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering
%B World Academy of Science, Engineering and Technology
%I International Science Index 120, 2016
%T Compensated CIC-Hybrid Signed Digit Decimation Filter
%U http://waset.org/publications/10007308
%V 120
%X In this paper, firstly, we present the mathematical modeling of finite impulse response (FIR) filter and Cascaded Integrator Comb (CIC) filter for sampling rate reduction and then an extension of Canonical signed digit (CSD) based efficient structure is presented in framework using hybrid signed digit (HSD) arithmetic. CSD representation imposed a restriction that two non-zero CSD coefficient bits cannot acquire adjacent bit positions and therefore, represented structure is not economical in terms of speed, area and power consumption. The HSD based structure gives optimum performance in terms of area and speed with 37.02% passband droop compensation.

%P 1497 - 1506