Ki-Jin Kim and Sanghoon Park and K. H. Ahn 20 GHz Fractional Phased Locked Loop Circuit for the Gbps Wireless Communication
1443 - 1446
2012
6
12
International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering http://waset.org/publications/15104
http://waset.org/publications/72
World Academy of Science, Engineering and Technology
This paper presents the 20GHz fractional PLL (Phase
Locked Loop) circuit for the next generation WiFi by using 90 nm
TSMC process. The newly suggested millimeter wave 1617
prescalar is designed and verified by measurement to make the
fractional PLL having a low quantization noise. The operational
bandwidth of the 60 GHz system is 15 of the carrier frequency
which requires large value of Kv (VCO control gain) resulting in
degradation of phase noise. To solve this problem, this paper adopts
AFC (Automatic Frequency Controller) controlled 4bit millimeter
wave VCO with small value of Kv. Also constant Kv is implemented
using 4bit varactor bank. The measured operational bandwidth is 18.2
23.2 GHz which is 25 of the carrier frequency. The phase noise of
58 and 96.2 dBcHz at 100 KHz and 1 MHz offset is measured
respectively. The total power consumption of the PLL is only 30 mW.
International Science Index 72, 2012