Scholarly Research Excellence
%0 Journal Article
%A Zulhelmi Zakaria and  Shuja A. Abbasi
%D 2013 
%J  International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering
%B World Academy of Science, Engineering and Technology
%I International Science Index 73, 2013
%T Optimized Multiplier Based upon 6-Input Luts and Vedic Mathematics
%U http://waset.org/publications/15168
%V 73
%X A new approach has been used for optimized design of multipliers based upon the concepts of Vedic mathematics. The design has been targeted to state-of-the art field-programmable gate arrays (FPGAs). The multiplier generates partial products using Vedic mathematics method by employing basic 4x4 multipliers designed by exploiting 6-input LUTs and multiplexers in the same slices resulting in drastic reduction in area. The multiplier is realized on Xilinx FPGAs using devices Virtex-5 and Virtex-6.Carry Chain Adder was employed to obtain final products. The performance of the proposed multiplier was examined and compared to well-known multipliers such as Booth, Carry Save, Carry ripple, and array multipliers. It is demonstrated that the proposed multiplier is superior in terms of speed as well as power consumption.

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