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Sharma, P. , Bhargava, B. , Akashe, S.. "Reduction of Leakage Power in Digital Logic Circuits Using Stacking Technique in 45 Nanometer Regime". World Academy of Science, Engineering and Technology, International Science Index 73, International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering (2013), 7(1), 60 - 65.