Scholarly Research Excellence
P.K. Sharma and  B. Bhargava and  S. Akashe,  Reduction of Leakage Power in Digital Logic Circuits Using Stacking Technique in 45 Nanometer Regime.   journal   = {International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering}, [online]. World Academy of Science, Engineering and Technology. January 2013, vol. 73(1). 60 - 65[viewed 20 November 2018]. Available from: http://waset.org/publications/17356.