Open Science Research Excellence
%0 Journal Article
%A N. Shen and  T. T. Le and  H. Y. Yu and  Z. X. Chen and  K. T. Win and  N. Singh and  G. Q. Lo and  D. -L. Kwong
%D 2011 
%J  International Journal of Chemical, Molecular, Nuclear, Materials and Metallurgical Engineering
%B World Academy of Science, Engineering and Technology
%I International Science Index 57, 2011
%T Fabrication and Characterization of Poly-Si Vertical Nanowire Thin Film Transistor
%U http://waset.org/publications/4635
%V 57
%X In this paper, we present a vertical nanowire thin film transistor with gate-all-around architecture, fabricated using CMOS compatible processes. A novel method of fabricating polysilicon vertical nanowires of diameter as small as 30 nm using wet-etch is presented. Both n-type and p-type vertical poly-silicon nanowire transistors exhibit superior electrical characteristics as compared to planar devices. On a poly-crystalline nanowire of 30 nm diameter, high Ion/Ioff ratio of 106, low drain-induced barrier lowering (DIBL) of 50 mV/V, and low sub-threshold slope SS~100mV/dec are demonstrated for a device with channel length of 100 nm.

%P 784 - 786