Open Science Research Excellence
@article{(International Science Index):,
  title    = {A Novel Four-Transistor SRAM Cell with Low Dynamic Power Consumption},
  author    = {Arash Azizi Mazreah and  Mohammad T. Manzuri Shalmani and  Hamid Barati and  Ali Barati},
  country   = {},
  abstract  = {This paper presents a novel CMOS four-transistor
SRAM cell for very high density and low power embedded SRAM
applications as well as for stand-alone SRAM applications. This cell
retains its data with leakage current and positive feedback without
refresh cycle. The new cell size is 20% smaller than a conventional
six-transistor cell using same design rules. Also proposed cell uses
two word-lines and one pair bit-line. Read operation perform from
one side of cell, and write operation perform from another side of
cell, and swing voltage reduced on word-lines thus dynamic power
during read/write operation reduced. The fabrication process is fully
compatible with high-performance CMOS logic technologies,
because there is no need to integrate a poly-Si resistor or a TFT load.
HSPICE simulation in standard 0.25μm CMOS technology confirms
all results obtained from this paper.},
    journal   = {International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering},  volume    = {2},
  number    = {3},
  year      = {2008},
  pages     = {351 - 355},
  ee        = {},
  url       = {},
  bibsource = {},
  issn      = {eISSN:1307-6892},
  publisher = {World Academy of Science, Engineering and Technology},
  index     = {International Science Index 15, 2008},