Motion Estimator Architecture with Optimized Number of Processing Elements for High Efficiency Video Coding
Motion estimation occupies the heaviest computation in HEVC (high efficiency video coding). Many fast algorithms such as TZS (test zone search) have been proposed to reduce the computation. Still the huge computation of the motion estimation is a critical issue in the implementation of HEVC video codec. In this paper, motion estimator architecture with optimized number of PEs (processing element) is presented by exploiting early termination. It also reduces hardware size by exploiting parallel processing. The presented motion estimator architecture has 8 PEs, and it can efficiently perform TZS with very high utilization of PEs.
 G. Sullivan, J. Ohm, W. Han, and T. Wiegand, “Overview of the High Efficiency Video Coding (HEVC) Standard”, IEEE Transactions on Circuits and Systems for Video Technology, vol. 22, no. 12, pp. 1649-1668, Dec. 2012.
 J. Lee and S. Lee, “8×8 HEVC Inverse Core Transform Architecture Using Multiplier Reuse”, Journal of IKEEE, vol. 17, no. 4, pp. 570-578, Dec. 2013.
 J. R. Jain and A. K. Jain, “Displacement measurement and its application in interframe image coding”, IEEE Transactions on Communications, vol. 29, no. 12, pp. 1799-1808, Dec. 1981.
 H. Jong, L. Chen, and T. Chiueh, "Parallel Architectures for 3-Step Hierarchical Search Block-Matching Algorithm," IEEE Transactions on Circuits and Systems for Video Technology, vol. 4, no. 4, pp. 407-416, Aug. 1994.
 H. Yang and S. Lee, “Motion Estimation Algorithm to Guarantee Hard Realtime Operation”, Journal of IKEEE, vol. 17, no. 1, pp. 36-43, Mar. 2013.
 X. Li, R. Wang, W. Wang, Z. Wang, and S. Dong, “Fast motion estimation methods for HEVC,” in Proc. of IEEE International Symposium on Broadband Multimedia Systems and Broadcasting, 2014, pp.1-4.