FPGA Implementation of Adaptive Clock Recovery for TDMoIP Systems
Circuit switched networks widely used until the end of the 20th century have been transformed into packages switched networks. Time Division Multiplexing over Internet Protocol (TDMoIP) is a system that enables Time Division Multiplexing (TDM) traffic to be carried over packet switched networks (PSN). In TDMoIP systems, devices that send TDM data to the PSN and receive it from the network must operate with the same clock frequency. In this study, it was aimed to implement clock synchronization process in Field Programmable Gate Array (FPGA) chips using time information attached to the packages received from PSN. The designed hardware is verified using the datasets obtained for the different carrier types and comparing the results with the software model. Field tests are also performed by using the real time TDMoIP system.
Circadian Clock and Subjective Time Perception: A Simple Open Source Application for the Analysis of Induced Time Perception in Humans
Subjective time perception implies connection to cognitive functions, attention, memory and awareness, but a little is known about connections with homeostatic states of the body coordinated by circadian clock. In this paper, we present results from experimental study of subjective time perception in volunteers performing physical activity on treadmill in various phases of their circadian rhythms. Subjects were exposed to several time illusions simulated by programmed timing systems. This study brings better understanding for further improvement of of work quality in isolated areas.
Two Kinds of Self-Oscillating Circuits Mechanically Demonstrated
This study introduces two types of self-oscillating
circuits that are frequently found in power electronics applications.
Special effort is made to relate the circuits to the analogous mechanical
systems of some important scientific inventions: Galileo’s pendulum
clock and Coulomb’s friction model. A little touch of related history
and philosophy of science will hopefully encourage curiosity, advance
the understanding of self-oscillating systems and satisfy the aspiration
of some students for scientific literacy. Finally, the two self-oscillating
circuits are applied to design a simple class-D audio amplifier.
Design and Optimization of Parity Generator and Parity Checker Based On Quantum-dot Cellular Automata
Quantum-dot Cellular Automata (QCA) is one of the most substitute emerging nanotechnologies for electronic circuits, because of lower power consumption, higher speed and smaller size in comparison with CMOS technology. The basic devices, a Quantum-dot cell can be used to implement logic gates and wires. As it is the fundamental building block on nanotechnology circuits. By applying XOR gate the hardware requirements for a QCA circuit can be decrease and circuits can be simpler in terms of level, delay and cell count. This article present a modest approach for implementing novel optimized XOR gate, which can be applied to design many variants of complex QCA circuits. Proposed XOR gate is simple in structure and powerful in terms of implementing any digital circuits. In order to verify the functionality of the proposed design some complex implementation of parity generator and parity checker circuits are proposed and simulating by QCA Designer tool and compare with some most recent design. Simulation results and physical relations confirm its usefulness in implementing every digital circuit.
A Novel FIFO Design for Data Transfer in Mixed Timing Systems
In the current scenario, with the increasing integration densities, most system-on-chip designs are partitioned into multiple clock domains. In this paper, an asynchronous FIFO (First-in First-out pipeline) design is employed as a data transfer interface between two independent clock domains. Since the clocks on the either sides of the FIFO run at a different speed, the task to ensure the correct data transmission through this FIFO is manually performed. Firstly an existing asynchronous FIFO design is discussed and simulated. Gate-level simulation results depicted the flaw in existing design. In order to solve this problem, a novel modified asynchronous FIFO design is proposed. The results obtained from proposed design are in perfect accordance with theoretical expectations. The proposed asynchronous FIFO design outperforms the existing design in terms of accuracy and speed. In order to evaluate the performance of the FIFO designs presented in this paper, the circuits were implemented in 0.24µ TSMC CMOS technology and simulated at 2.5V using HSpice (© Avant! Corporation). The layout design of the proposed FIFO is also presented.
Design and Implementation of Quantum Cellular Automata Based Novel Adder Circuits
The most important mathematical operation for any computing system is addition. An efficient adder can be of greater assistance in designing of any arithmetic circuits. Quantum-dot Cellular Automata (QCA) is a promising nanotechnology to create electronic circuits for computing devices and suitable candidate for next generation of computing systems. The article presents a modest approach to implement a novel XOR gate. The gate is simple in structure and powerful in terms of implementing digital circuits. By applying the XOR gate, the hardware requirement for a QCA circuit can be decrease and circuits can be simpler in level, clock phase and cell count. In order to verify the functionality of the proposed device some implementation of Half Adder (HA) and Full Adder (FA) is checked by means of computer simulations using QCA-Designer tool. Simulation results and physical relations confirm its usefulness in implementing every digital circuit.
Design and Analysis of a Low Power High Speed 1 Bit Full Adder Cell Based On TSPC Logic with Multi-Threshold CMOS
An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high threshold voltage sleep transistor is used to reduce the static power dissipation in standby mode. The circuit is designed and simulated in TSPICE using TSMC 180nm CMOS process. Average power consumption, delay and power-delay product is measured which showed considerable improvement in performance over the existing full adder designs.
An Energy Efficient Digital Baseband for Batteryless Remote Control
In this paper, an energy efficient digital baseband circuit for piezoelectric (PE) harvester powered batteryless remote control system is presented. Pulse mode PE harvester, which provides short duration of energy, is adopted to replace conventional chemical battery in wireless remote controller. The transmitter digital baseband repeats the control command transmission once the digital circuit is initiated by the power-on-reset. A power efficient data frame format is proposed to maximize the transmission repetition time. By using the proposed frame format and receiver clock and data recovery method, the receiver baseband is able to decode the command even when the received data has 20% error. The proposed transmitter and receiver baseband are implemented using FPGA and simulation results are presented.
Complementary Energy Path Adiabatic Logic based Full Adder Circuit
In this paper, we present the design and experimental
evaluation of complementary energy path adiabatic logic (CEPAL)
based 1 bit full adder circuit. A simulative investigation on the
proposed full adder has been done using VIRTUOSO SPECTRE
simulator of cadence in 0.18μm UMC technology and its
performance has been compared with the conventional CMOS full
adder circuit. The CEPAL based full adder circuit exhibits the energy
saving of 70% to the conventional CMOS full adder circuit, at 100
MHz frequency and 1.8V operating voltage.
Quantum Dot Cellular Automata Based Effective Design of Combinational and Sequential Logical Structures
The use of Quantum dots is a promising emerging
Technology for implementing digital system at the nano level. It is
effecient for attractive features such as faster speed , smaller size and
low power consumption than transistor technology. In this paper,
various Combinational and sequential logical structures - HALF
ADDER, SR Latch and Flip-Flop, D Flip-Flop preceding NAND,
NOR, XOR,XNOR are discussed based on QCA design, with
comparatively less number of cells and area. By applying these
layouts, the hardware requirements for a QCA design can be reduced.
These structures are designed and simulated using QCA Designer
Tool. By taking full advantage of the unique features of this
technology, we are able to create complete circuits on a single layer
of QCA. Such Devices are expected to function with ultra low
power Consumption and very high speeds.
Fatigue Life Consumption for Turbine Blades-Vanes Accelerated by Erosion-Contour Modification
A new mechanism responsible for structural life
consumption due to resonant fatigue in turbine blades, or vanes, is
presented and explained. A rotating blade or vane in a gas turbine can
change its contour due to erosion and/or material build up, in any of
these instances, the surface pressure distribution occurring on the
suction and pressure sides of blades-vanes can suffer substantial
modification of their pressure and temperatures envelopes and flow
characteristics. Meanwhile, the relative rotation between the blade
and duct vane while the pressurized gas flows and the consequent
wake crossings, will induce a fluctuating thrust force or lift that will
excite the blade.
An actual totally used up set of vane-blade components in a HP
turbine power stage in a gas turbine is analyzed. The blade suffered
some material erosion mostly at the trailing edge provoking a
peculiar surface pressure envelope which evolved as the relative
position between the vane and the blade passed in front of each other.
Interestingly preliminary modal analysis for this eroded blade
indicates several natural frequencies within the aeromechanic power
spectrum, moreover, the highest frequency component is 94% of one
natural frequency indicating near resonant condition.
Independently of other simultaneously occurring fatigue cycles
(such as thermal, centrifugal stresses).
A Clock Skew Minimization Technique Considering Temperature Gradient
The trend of growing density on chips has increases not
only the temperature in chips but also the gradient of the temperature
depending on locations. In this paper, we propose the balanced skew
tree generation technique for minimizing the clock skew that is
affected by the temperature gradients on chips. We calculate the
interconnect delay using Elmore delay equation, and find out the
optimal balanced clock tree by modifying the clock trees generated
through the Deferred Merge Embedding(DME) algorithm. The
experimental results show that the distance variance of clock insertion
points with and without considering the temperature gradient can be
lowered below 54% and we confirm that the skew is remarkably
decreased after applying the proposed technique.
Modeling of a Second Order Non-Ideal Sigma-Delta Modulator
A behavioral model of a second order switchedcapacitor Sigma-Delta modulator is presented. The purpose of this work is the presentation of a behavioral model of a second order switched capacitor ΣΔ modulator considering (Error due to Clock Jitter, Thermal noise Amplifier Noise, Amplifier Slew-Rate, Non linearity of amplifiers, Gain error, Charge Injection, Clock Feedthrough, and Nonlinear on-resistance). A comparison between the use of MOS switches and the use transmission gate switches use is analyzed.
Effect of Magnetic Field on the Biological Clock through the Radical Pair Mechanism
There is an ongoing controversy in the literature related
to the biological effects of weak, low frequency electromagnetic
fields. The physical arguments and interpretation of the experimental
evidence are inconsistent, where some physical arguments and
experimental demonstrations tend to reject the likelihood of any
effect of the fields at extremely low level. The problem arises of
explaining, how the low-energy influences of weak magnetic fields
can compete with the thermal and electrical noise of cells at normal
temperature using the theoretical studies. The magnetoreception in
animals involve radical pair mechanism. The same mechanism has
been shown to be involved in the circadian rhythm synchronization in
mammals. These reactions can be influenced by the weak magnetic
fields. Hence, it is postulated the biological clock can be affected
by weak magnetic fields and these disruptions to the rhythm can
cause adverse biological effects. In this paper, likelihood of altering
the biological clock via the radical pair mechanism is analyzed to
simplify these studies of controversy.
A Single-Phase Register File with Complementary Pass-Transistor Adiabatic Logic
This paper introduces an adiabatic register file based
on two-phase CPAL (Complementary Pass-Transistor Adiabatic
Logic circuits) with power-gating scheme, which can operate on a
single-phase power clock. A 32×32 single-phase adiabatic register file
with power-gating scheme has been implemented with TSMC 0.18μm
CMOS technology. All the circuits except for the storage cells employ
two-phase CPAL circuits, and the storage cell is based on the
conventional memory one. The two-phase non-overlap power-clock
generator with power-gating scheme is used to supply the proposed
adiabatic register file. Full-custom layouts are drawn. The energy and
functional simulations have been performed using the net-list
extracted from their layouts. Compared with the traditional static
CMOS register file, HSPICE simulations show that the proposed
adiabatic register file can work very well, and it attains about 73%
energy savings at 100 MHz.
64 bit Computer Architectures for Space Applications – A study
The more recent satellite projects/programs makes
extensive usage of real – time embedded systems. 16 bit processors
which meet the Mil-Std-1750 standard architecture have been used in
on-board systems. Most of the Space Applications have been written
in ADA. From a futuristic point of view, 32 bit/ 64 bit processors are
needed in the area of spacecraft computing and therefore an effort is
desirable in the study and survey of 64 bit architectures for space
applications. This will also result in significant technology
development in terms of VLSI and software tools for ADA (as the
legacy code is in ADA).
There are several basic requirements for a special processor for
this purpose. They include Radiation Hardened (RadHard) devices,
very low power dissipation, compatibility with existing operational
systems, scalable architectures for higher computational needs,
reliability, higher memory and I/O bandwidth, predictability, realtime
operating system and manufacturability of such processors.
Further on, these may include selection of FPGA devices, selection
of EDA tool chains, design flow, partitioning of the design, pin
count, performance evaluation, timing analysis etc.
This project deals with a brief study of 32 and 64 bit processors
readily available in the market and designing/ fabricating a 64 bit
RISC processor named RISC MicroProcessor with added
functionalities of an extended double precision floating point unit
and a 32 bit signal processing unit acting as co-processors. In this
paper, we emphasize the ease and importance of using Open Core
(OpenSparc T1 Verilog RTL) and Open “Source" EDA tools such as
Icarus to develop FPGA based prototypes quickly. Commercial tools
such as Xilinx ISE for Synthesis are also used when appropriate.
Jitter Transfer in High Speed Data Links
Phase locked loops for data links operating at 10 Gb/s
or faster are low phase noise devices designed to operate with a low
jitter reference clock. Characterization of their jitter transfer function
is difficult because the intrinsic noise of the device is comparable to
the random noise level in the reference clock signal. A linear model
is proposed to account for the intrinsic noise of a PLL. The intrinsic
noise data of a PLL for 10 Gb/s links is presented. The jitter transfer
function of a PLL in a test chip for 12.8 Gb/s data links was
determined in experiments using the 400 MHz reference clock as the
source of simultaneous excitations over a wide range of frequency.
The result shows that the PLL jitter transfer function can be
approximated by a second order linear model.
Phase Jitter Transfer in High Speed Data Links
Phase locked loops in 10 Gb/s and faster data links are
low phase noise devices. Characterization of their phase jitter
transfer functions is difficult because the intrinsic noise of the PLLs
is comparable to the phase noise of the reference clock signal. The
problem is solved by using a linear model to account for the intrinsic
noise. This study also introduces a novel technique for measuring the
transfer function. It involves the use of the reference clock as a
source of wideband excitation, in contrast to the commonly used
sinusoidal excitations at discrete frequencies. The data reported here
include the intrinsic noise of a PLL for 10 Gb/s links and the jitter
transfer function of a PLL for 12.8 Gb/s links. The measured transfer
function suggests that the PLL responded like a second order linear
system to a low noise reference clock.
A 24-Bit, 8.1-MS/s D/A Converter for Audio Baseband Channel Applications
This paper study the high-level modelling and design
of delta-sigma (ΔΣ) noise shapers for audio Digital-to-Analog
Converter (DAC) so as to eliminate the in-band Signal-to-Noise-
Ratio (SNR) degradation that accompany one channel mismatch in
audio signal. The converter combines a cascaded digital signal
interpolation, a noise-shaping single loop delta-sigma modulator with
a 5-bit quantizer resolution in the final stage. To reduce sensitivity of
Digital-to-Analog Converter (DAC) nonlinearities of the last stage, a
high pass second order Data Weighted Averaging (R2DWA) is
introduced. This paper presents a MATLAB description modelling
approach of the proposed DAC architecture with low distortion and
swing suppression integrator designs. The ΔΣ Modulator design can
be configured as a 3rd-order and allows 24-bit PCM at sampling rate
of 64 kHz for Digital Video Disc (DVD) audio application. The
modeling approach provides 139.38 dB of dynamic range for a 32
kHz signal band at -1.6 dBFS input signal level.
A New Digital Transceiver Circuit for Asynchronous Communication
A new digital transceiver circuit for asynchronous frame detection is proposed where both the transmitter and receiver contain all digital components, thereby avoiding possible use of conventional devices like monostable multivibrators with unstable external components such as resistances and capacitances. The proposed receiver circuit, in particular, uses a combinational logic block yielding an output which changes its state as soon as the start bit of a new frame is detected. This, in turn, helps in generating an efficient receiver sampling clock. A data latching circuit is also used in the receiver to latch the recovered data bits in any new frame. The proposed receiver structure is also extended from 4- bit information to any general n data bits within a frame with a common expression for the output of the combinational logic block. Performance of the proposed hardware design is evaluated in terms of time delay, reliability and robustness in comparison with the standard schemes using monostable multivibrators. It is observed from hardware implementation that the proposed circuit achieves almost 33 percent speed up over any conventional circuit.
A 3.125Gb/s Clock and Data Recovery Circuit Using 1/4-Rate Technique
This paper describes the design and fabrication of a clock and data recovery circuit (CDR). We propose a new clock and data recovery which is based on a 1/4-rate frequency detector (QRFD). The proposed frequency detector helps reduce the VCO frequency and is thus advantageous for high speed application. The proposed frequency detector can achieve low jitter operation and extend the pull-in range without using the reference clock. The proposed CDR was implemented using a 1/4-rate bang-bang type phase detector (PD) and a ring voltage controlled oscillator (VCO). The CDR circuit has been fabricated in a standard 0.18 CMOS technology. It occupies an active area of 1 x 1 and consumes 90 mW from a single 1.8V supply.