Open Science Research Excellence

Open Science Index

Commenced in January 2007 Frequency: Monthly Edition: International Paper Count: 23

Image Rotation Using an Augmented 2-Step Shear Transform
Image rotation is one of main pre-processing steps for image processing or image pattern recognition. It is implemented with a rotation matrix multiplication. It requires a lot of floating point arithmetic operations and trigonometric calculations, so it takes a long time to execute. Therefore, there has been a need for a high speed image rotation algorithm without two major time-consuming operations. However, the rotated image has a drawback, i.e. distortions. We solved the problem using an augmented two-step shear transform. We compare the presented algorithm with the conventional rotation with images of various sizes. Experimental results show that the presented algorithm is superior to the conventional rotation one.
Tool Condition Monitoring of Ceramic Inserted Tools in High Speed Machining through Image Processing
Cutting tools with ceramic inserts are often used in the process of machining many types of superalloy, mainly due to their high strength and thermal resistance. Nevertheless, during the cutting process, the plastic flow wear generated in these inserts enhances and propagates cracks due to high temperature and high mechanical stress. This leads to a very variable failure of the cutting tool. This article explores the relationship between the continuous wear that ceramic SiAlON (solid solutions based on the Si3N4 structure) inserts experience during a high-speed machining process and the evolution of sparks created during the same process. These sparks were analysed through pictures of the cutting process recorded using an SLR camera. Features relating to the intensity and area of the cutting sparks were extracted from the individual pictures using image processing techniques. These features were then related to the ceramic insert’s crater wear area.
Experimental Investigation of Indirect Field Oriented Control of Field Programmable Gate Array Based Five-Phase Induction Motor Drive

This paper analyzes the experimental investigation of indirect field oriented control of Field Programmable Gate Array (FPGA) based five-phase induction motor drive. A detailed d-q modeling and Space Vector Pulse Width Modulation (SVPWM) technique of 5-phase drive is elaborated in this paper. In the proposed work, the prototype model of 1 hp 5-phase Voltage Source Inverter (VSI) fed drive is implemented in hardware. SVPWM pulses are generated in FPGA platform through Very High Speed Integrated Circuit Hardware Description Language (VHDL) coding. The experimental results are observed under different loading conditions and compared with simulation results to validate the simulation model.

Carbide Structure and Fracture Toughness of High Speed Tool Steels

In the present study, M2 high speed steels were fabricated by using electro-slag rapid remelting process. Carbide structure was analysed and the fracture toughness and hardness were also measured after austenitization treatment at 1190 and 1210oC followed by tempering treatment at 535oC for billets with various diameters from 16 to 60 mm. Electro-slag rapid remelting (ESRR) process is an advanced ESR process combined by continuous casting and successfully employed in this study to fabricate a sound M2 high speed ingot. Three other kinds of commercial M2 high speed steels, produced by traditional method, were also analysed for comparison. Distribution and structure of eutectic carbides of the ESRR billet were found to be comparable to those of commercial alloy and so was the fracture toughness.

Neural Network Monitoring Strategy of Cutting Tool Wear of Horizontal High Speed Milling

The wear of cutting tool degrades the quality of the product in the manufacturing processes. The on line monitoring of the cutting tool wear level is very necessary to prevent the deterioration of the quality of machining. Unfortunately there is not a direct manner to measure the cutting tool wear on line. Consequently we must adopt an indirect method where wear will be estimated from the measurement of one or more physical parameters appearing during the machining process such as the cutting force, the vibrations, or the acoustic emission etc…. In this work, a neural network system is elaborated in order to estimate the flank wear from the cutting force measurement and the cutting conditions.

Alloying Effect on Hot Workability of M42 High Speed Steel

In the present study, the effect of Si, Al, Ti, Zr, and Nb addition on the microstructure and hot workability of cast M42 tool steels, basically consisting of 1.0C, 0.2Mn, 3.8Cr, 1.5W, 8.5Co, 9.2Mo, and 1.0V in weight percent has been investigated. Tool steels containing Si of 0.25 and 0.5wt.%, Al of 0.06 and 0.12wt.%, Ti of 0.3wt.%, Zr of 0.3wt.%, and Nb of 0.3wt.% were cast into ingots of 140mm ´ 140mm ´ 330mm by vacuum induction melting. After solution treatment at 1150oC for 1.5hr followed by furnace cooling, hot rolling at 1180oC was conducted on the ingots. Addition of titanium, zirconium and niobium was found to retard the decomposition of the eutectic carbides and result in the deterioration of hot workability of the tool steels, while addition of aluminum and silicon showed relatively well decomposed carbide structure and resulted in sound hot rolled plates.

A Very High Speed, High Resolution Current Comparator Design

This paper presents an idea for analog current comparison which compares input signal and reference currents with high speed and accuracy. Proposed circuit utilizes amplification properties of common gate configuration, where voltage variations of input current are amplified and a compared output voltage is developed. Cascaded inverter stages are used to generate final CMOS compatible output voltage. Power consumption of circuit can be controlled by the applied gate bias voltage. The comparator is designed and studied at 180nm CMOS process technology for a supply voltage of 3V.

The Suitability of GPS Receivers Update Rates for Navigation Applications
Navigation is the processes of monitoring and controlling the movement of an object from one place to another. Currently, Global Positioning System (GPS) is the main navigation system used all over the world for navigation applications. GPS receiver receives signals from at least three satellites to locate and display itself. Displayed positioning information is updated continuously. Update rate is the number of times per second that a display is illuminated. The speed of update is governed by receiver update rate. A higher update rate decreases display lag time and improves distance measurements and tracking especially when moving on a curvy route. The majority of GPS receivers used nowadays are updated every second continuously. This period is considered reasonable for some applications while it is long relatively for high speed applications. In this paper, the suitability and feasibility of GPS receiver with different update rates will be evaluated for various applications according to the level of speed and update rate needed for particular applications.
Preparation and Characterization of Nylon 6-Clay Hybrid/Neat Nylon 6 Bicomponent Nanocomposite Fibers
Nylon 6-clay hybrid/neat nylon 6, sheath/core bicomponent nanocomposite fibers containing 4 wt% of clay in sheath section were melt spun at different take-up speeds. Their orientation and crystalline structure were compared to those of neat nylon 6 fibers. Birefringence measurements showed that the orientation development in sheath and core parts of bicomponent fibers was different. Crystallinity results showed that clay did not act as a nucleating agent for bicomponent fibers. The neat nylon 6 fiber had a smooth surface while striped pattern was appeared on the surface of bicomponent fiber containing clay due to thermal shrinkage of the core part.
Image Sensor Matrix High Speed Simulation

This paper presents a new high speed simulation methodology to solve the long simulation time problem of CMOS image sensor matrix. Generally, for integrating the pixel matrix in SOC and simulating the system performance, designers try to model the pixel in various modeling languages such as VHDL-AMS, SystemC or Matlab. We introduce a new alternative method based on spice model in cadence design platform to achieve accuracy and reduce simulation time. The simulation results indicate that the pixel output voltage maximum error is at 0.7812% and time consumption reduces from 2.2 days to 13 minutes achieving about 240X speed-up for the 256x256 pixel matrix.

Investigation of the Effect of Cavitator Angle and Dimensions for a Supercavitating Vehicle

At very high speeds, bubbles form in the underwater vehicles because of sharp trailing edges or of places where the local pressure is lower than the vapor pressure. These bubbles are called cavities and the size of the cavities grows as the velocity increases. A properly designed cavitator can induce the formation of a single big cavity all over the vehicle. Such a vehicle travelling in the vaporous cavity is called a supercavitating vehicle and the present research work mainly focuses on the dynamic modeling of such vehicles. Cavitation of the fins is also accounted and the effect of the same on trajectory is well explained. The entire dynamics has been developed using the state space approach and emphasis is given on the effect of size and angle of attack of the cavitator. Control law has been established for the motion of the vehicle using Non-linear Dynamic Inverse (NDI) with cavitator as the control surface.

Some Design Issues in Designing of 50KW 50Krpm Permanent Magnet Synchronous Machine
A numbers of important developments have led to an increasing attractiveness for very high speed electrical machines (either motor or generator). Specifically the increasing switching speed of power electronics, high energy magnets, high strength retaining materials, better high speed bearings and improvements in design analysis are the primary drivers in a move to higher speed. The design challenges come in the mechanical design both in terms of strength and resonant modes and in the electromagnetic design particularly in respect of iron losses and ac losses in the various conducting parts including the rotor. This paper describes detailed design work which has been done on a 50,000 rpm, 50kW permanent magnet( PM) synchronous machine. It describes work on electromagnetic and rotor eddy current losses using a variety of methods including both 2D finite element analysis
Analysis of Residual Strain and Stress Distributions in High Speed Milled Specimens using an Indentation Method
Through a proper analysis of residual strain and stress distributions obtained at the surface of high speed milled specimens of AA 6082–T6 aluminium alloy, the performance of an improved indentation method is evaluated. This method integrates a special device of indentation to a universal measuring machine. The mentioned device allows introducing elongated indents allowing to diminish the absolute error of measurement. It must be noted that the present method offers the great advantage of avoiding both the specific equipment and highly qualified personnel, and their inherent high costs. In this work, the cutting tool geometry and high speed parameters are selected to introduce reduced plastic damage. Through the variation of the depth of cut, the stability of the shapes adopted by the residual strain and stress distributions is evaluated. The results show that the strain and stress distributions remain unchanged, compressive and small. Moreover, these distributions reveal a similar asymmetry when the gradients corresponding to conventional and climb cutting zones are compared.
Automatic Inspection of Percussion Caps by Means of Combined 2D and 3D Machine Vision Techniques
The exhaustive quality control is becoming more and more important when commercializing competitive products in the world's globalized market. Taken this affirmation as an undeniable truth, it becomes critical in certain sector markets that need to offer the highest restrictions in quality terms. One of these examples is the percussion cap mass production, a critical element assembled in firearm ammunition. These elements, built in great quantities at a very high speed, must achieve a minimum tolerance deviation in their fabrication, due to their vital importance in firing the piece of ammunition where they are built in. This paper outlines a machine vision development for the 100% inspection of percussion caps obtaining data from 2D and 3D simultaneous images. The acquisition speed and precision of these images from a metallic reflective piece as a percussion cap, the accuracy of the measures taken from these images and the multiple fabrication errors detected make the main findings of this work.
400 kW Six Analytical High Speed Generator Designs for Smart Grid Systems
High Speed PM Generators driven by micro-turbines are widely used in Smart Grid System. So, this paper proposes comparative study among six classical, optimized and genetic analytical design cases for 400 kW output power at tip speed 200 m/s. These six design trials of High Speed Permanent Magnet Synchronous Generators (HSPMSGs) are: Classical Sizing; Unconstrained optimization for total losses and its minimization; Constrained optimized total mass with bounded constraints are introduced in the problem formulation. Then a genetic algorithm is formulated for obtaining maximum efficiency and minimizing machine size. In the second genetic problem formulation, we attempt to obtain minimum mass, the machine sizing that is constrained by the non-linear constraint function of machine losses. Finally, an optimum torque per ampere genetic sizing is predicted. All results are simulated with MATLAB, Optimization Toolbox and its Genetic Algorithm. Finally, six analytical design examples comparisons are introduced with study of machines waveforms, THD and rotor losses.
Influence of High Speed Parameters on the Quality of Machined Surface

The contribution is dealing with the influence of high speed parameters on the quality of machined surface. In general the principle of high speed cutting lies in achieving faster machine times with concurrent increase in accuracy and quality of the machined areas in largely irregular, mathematically hard to define shapes. High speed machining is a highly effective method of machining with the following goals: increasing of machining productivity, increasing of quality of the machined surface, improving of machining economy, improving of ecological aspects of machining. This article is based on an experiment performed by the Department of Machining and Assembly of the Faculty of Mechanical Engineering of VŠBTechnical University of Ostrava.

New Design Methodologies for High Speed Low Power XOR-XNOR Circuits
New methodologies for XOR-XNOR circuits are proposed to improve the speed and power as these circuits are basic building blocks of many arithmetic circuits. This paper evaluates and compares the performance of various XOR-XNOR circuits. The performance of the XOR-XNOR circuits based on TSMC 0.18μm process models at all range of the supply voltage starting from 0.6V to 3.3V is evaluated by the comparison of the simulation results obtained from HSPICE. Simulation results reveal that the proposed circuit exhibit lower PDP and EDP, more power efficient and faster when compared with best available XOR-XNOR circuits in the literature.
An Enhanced Distributed System to improve theTime Complexity of Binary Indexed Trees

Distributed Computing Systems are usually considered the most suitable model for practical solutions of many parallel algorithms. In this paper an enhanced distributed system is presented to improve the time complexity of Binary Indexed Trees (BIT). The proposed system uses multi-uniform processors with identical architectures and a specially designed distributed memory system. The analysis of this system has shown that it has reduced the time complexity of the read query to O(Log(Log(N))), and the update query to constant complexity, while the naive solution has a time complexity of O(Log(N)) for both queries. The system was implemented and simulated using VHDL and Verilog Hardware Description Languages, with xilinx ISE 10.1, as the development environment and ModelSim 6.1c, similarly as the simulation tool. The simulation has shown that the overhead resulting by the wiring and communication between the system fragments could be fairly neglected, which makes it applicable to practically reach the maximum speed up offered by the proposed model.

Low Power and Less Area Architecture for Integer Motion Estimation

Full search block matching algorithm is widely used for hardware implementation of motion estimators in video compression algorithms. In this paper we are proposing a new architecture, which consists of a 2D parallel processing unit and a 1D unit both working in parallel. The proposed architecture reduces both data access power and computational power which are the main causes of power consumption in integer motion estimation. It also completes the operations with nearly the same number of clock cycles as compared to a 2D systolic array architecture. In this work sum of absolute difference (SAD)-the most repeated operation in block matching, is calculated in two steps. The first step is to calculate the SAD for alternate rows by a 2D parallel unit. If the SAD calculated by the parallel unit is less than the stored minimum SAD, the SAD of the remaining rows is calculated by the 1D unit. Early termination, which stops avoidable computations has been achieved with the help of alternate rows method proposed in this paper and by finding a low initial SAD value based on motion vector prediction. Data reuse has been applied to the reference blocks in the same search area which significantly reduced the memory access.

Jitter Transfer in High Speed Data Links
Phase locked loops for data links operating at 10 Gb/s or faster are low phase noise devices designed to operate with a low jitter reference clock. Characterization of their jitter transfer function is difficult because the intrinsic noise of the device is comparable to the random noise level in the reference clock signal. A linear model is proposed to account for the intrinsic noise of a PLL. The intrinsic noise data of a PLL for 10 Gb/s links is presented. The jitter transfer function of a PLL in a test chip for 12.8 Gb/s data links was determined in experiments using the 400 MHz reference clock as the source of simultaneous excitations over a wide range of frequency. The result shows that the PLL jitter transfer function can be approximated by a second order linear model.
Low Jitter ADPLL based Clock Generator for High Speed SoC Applications
An efficient architecture for low jitter All Digital Phase Locked Loop (ADPLL) suitable for high speed SoC applications is presented in this paper. The ADPLL is designed using standard cells and described by Hardware Description Language (HDL). The ADPLL implemented in a 90 nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. The simulation result shows that PLL has cycle to cycle jitter of 164 ps and period jitter of 100 ps at 100MHz. Since the digitally controlled oscillator (DCO) can achieve both high resolution and wide frequency range, it can meet the demands of system-level integration. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for System-on-Chip (SoC) applications.
Phase Jitter Transfer in High Speed Data Links
Phase locked loops in 10 Gb/s and faster data links are low phase noise devices. Characterization of their phase jitter transfer functions is difficult because the intrinsic noise of the PLLs is comparable to the phase noise of the reference clock signal. The problem is solved by using a linear model to account for the intrinsic noise. This study also introduces a novel technique for measuring the transfer function. It involves the use of the reference clock as a source of wideband excitation, in contrast to the commonly used sinusoidal excitations at discrete frequencies. The data reported here include the intrinsic noise of a PLL for 10 Gb/s links and the jitter transfer function of a PLL for 12.8 Gb/s links. The measured transfer function suggests that the PLL responded like a second order linear system to a low noise reference clock.
VFAST TCP: A delay-based enhanced version of FAST TCP
This paper is aimed at describing a delay-based endto- end (e2e) congestion control algorithm, called Very FAST TCP (VFAST), which is an enhanced version of FAST TCP. The main idea behind this enhancement is to smoothly estimate the Round-Trip Time (RTT) based on a nonlinear filter, which eliminates throughput and queue oscillation when RTT fluctuates. In this context, an evaluation of the suggested scheme through simulation is introduced, by comparing our VFAST prototype with FAST in terms of throughput, queue behavior, fairness, stability, RTT and adaptivity to changes in network. The achieved simulation results indicate that the suggested protocol offer better performance than FAST TCP in terms of RTT estimation and throughput.
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