|Commenced in January 2007||Frequency: Monthly||Edition: International||Paper Count: 12|
In this paper we focus on the Round Trip Delay (RTD) time measurement technique which is an easy way to obtain the operating condition information in wireless network (WN). RTD measurement is affected by various parameters of wireless network. We illustrate how these RTD parameters vary (in a telemanagement application) versus distance, baud rates, number of hops, between nodes, using radio modem & router unit as a means of transmission and wireless routing.
This paper presents the design, implementation and evaluation of a micro-network, or Network-on-Chip (NoC), based on a generic pipeline router architecture. The router is designed to efficiently support traffic generated by multimedia applications on embedded multi-core systems. It employs a simplest routing mechanism and implements the round-robin scheduling strategy to resolve output port contentions and minimize latency. A virtual channel flow control is applied to avoid the head-of-line blocking problem and enhance performance in the NoC. The hardware design of the router architecture has been implemented at the register transfer level; its functionality is evaluated in the case of the two dimensional Mesh/Torus topology, and performance results are derived from ModelSim simulator and Xilinx ISE 9.2i synthesis tool. An example of a multi-core image processing system utilizing the NoC structure has been implemented and validated to demonstrate the capability of the proposed micro-network architecture. To reduce complexity of the image compression and decompression architecture, the system use image processing algorithm based on classical discrete cosine transform with an efficient zonal processing approach. The experimental results have confirmed that both the proposed image compression scheme and NoC architecture can achieve a reasonable image quality with lower processing time.
Internet is without any doubt the fastest and effective mean of communication making it possible to reach a great number of people in the world. It draws its base from exchange points. Indeed exchange points are used to inter-connect various Internet suppliers and operators in order to allow them to exchange traffic and it is with these interconnections that Internet made its great strides. They thus make it possible to limit the traffic delivered via the operators of transits. This limitation allows a significant improvement of the quality of service, a reduction in the latency time just as a reduction of the cost of connection for the final subscriber. Through this article we will show how the installation of an IXP allows an improvement and a diversification of the services just as a reduction of the Internet connection costs.
The Globally Asynchronous Locally Synchronous Network on Chip (GALS NoC) is the most efficient solution that provides low latency transfers and power efficient System on Chip (SoC) interconnect. This study presents a GALS and generic NoC architecture based on a configurable router. This router integrates a sophisticated dynamic arbiter, the wormhole routing technique and can be configured in a manner that allows it to be used in many possible NoC topologies such as Mesh 2-D, Tree and Polygon architectures. This makes it possible to improve the quality of service (QoS) required by the proposed NoC. A comparative performances study of the proposed NoC architecture, Tore architecture and of the most used Mesh 2D architecture is performed. This study shows that Spidergon architecture is characterised by the lower latency and the later saturation. It is also shown that no matter what the number of used links is raised; the Links×Diameter product permitted by the Spidergon architecture remains always the lower. The only limitation of this architecture comes from it-s over cost in term of silicon area.