Open Science Research Excellence

Open Science Index

Commenced in January 2007 Frequency: Monthly Edition: International Paper Count: 8

8
10005811
Design of Local Interconnect Network Controller for Automotive Applications
Abstract:

Local interconnect network (LIN) is a communication protocol that combines sensors, actuators, and processors to a functional module in automotive applications. In this paper, a LIN ver. 2.2A controller was designed in Verilog hardware description language (Verilog HDL) and implemented in field-programmable gate array (FPGA). Its operation was verified by making full-scale LIN network with the presented FPGA-implemented LIN controller, commercial LIN transceivers, and commercial processors. When described in Verilog HDL and synthesized in 0.18 μm technology, its gate size was about 2,300 gates.

7
10001612
An Optimization Tool-Based Design Strategy Applied to Divide-by-2 Circuits with Unbalanced Loads
Abstract:
This paper describes an optimization tool-based design strategy for a Current Mode Logic CML divide-by-2 circuit. Representing a building block for output frequency generation in a RFID protocol based-frequency synthesizer, the circuit was designed to minimize the power consumption for driving of multiple loads with unbalancing (at transceiver level). Implemented with XFAB XC08 180 nm technology, the circuit was optimized through MunEDA WiCkeD tool at Cadence Virtuoso Analog Design Environment ADE.
6
10003986
H.263 Based Video Transceiver for Wireless Camera System
Authors:
Abstract:
In this paper, a design of H.263 based wireless video transceiver is presented for wireless camera system. It uses standard WIFI transceiver and the covering area is up to 100m. Furthermore the standard H.263 video encoding technique is used for video compression since wireless video transmitter is unable to transmit high capacity raw data in real time and the implemented system is capable of streaming at speed of less than 1Mbps using NTSC 720x480 video.
5
15104
20 GHz Fractional Phased Locked Loop Circuit for the Gbps Wireless Communication
Abstract:
This paper presents the 20-GHz fractional PLL (Phase Locked Loop) circuit for the next generation Wi-Fi by using 90 nm TSMC process. The newly suggested millimeter wave 16/17 pre-scalar is designed and verified by measurement to make the fractional PLL having a low quantization noise. The operational bandwidth of the 60 GHz system is 15 % of the carrier frequency which requires large value of Kv (VCO control gain) resulting in degradation of phase noise. To solve this problem, this paper adopts AFC (Automatic Frequency Controller) controlled 4-bit millimeter wave VCO with small value of Kv. Also constant Kv is implemented using 4-bit varactor bank. The measured operational bandwidth is 18.2 ~ 23.2 GHz which is 25 % of the carrier frequency. The phase noise of -58 and -96.2 dBc/Hz at 100 KHz and 1 MHz offset is measured respectively. The total power consumption of the PLL is only 30 mW.
4
11500
Low Power Digital System for Reconfigurable Neural Recording System
Abstract:
A digital system is proposed for low power 100- channel neural recording system in this paper, which consists of 100 amplifiers, 100 analog-to-digital converters (ADC), digital controller and baseband, transceiver for data link and RF command link. The proposed system is designed in a 0.18 μm CMOS process and 65 nm CMOS process.
3
15067
Mitigation of Radiation Levels for Base Transceiver Stations based on ITU-T Recommendation K.70
Abstract:

This essay presents applicative methods to reduce human exposure levels in the area around base transceiver stations in a environment with multiple sources based on ITU-T recommendation K.70. An example is presented to understand the mitigation techniques and their results and also to learn how they can be applied, especially in developing countries where there is not much research on non-ionizing radiations.

2
9059
Decimation Filter Design Toolbox for Multi-Standard Wireless Transceivers using MATLAB
Abstract:

The demand for new telecommunication services requiring higher capacities, data rates and different operating modes have motivated the development of new generation multi-standard wireless transceivers. A multi-standard design often involves extensive system level analysis and architectural partitioning, typically requiring extensive calculations. In this research, a decimation filter design tool for wireless communication standards consisting of GSM, WCDMA, WLANa, WLANb, WLANg and WiMAX is developed in MATLAB® using GUIDE environment for visual analysis. The user can select a required wireless communication standard, and obtain the corresponding multistage decimation filter implementation using this toolbox. The toolbox helps the user or design engineer to perform a quick design and analysis of decimation filter for multiple standards without doing extensive calculation of the underlying methods.

1
1269
Design Optimization Methodology of CMOS Active Mixers for Multi-Standard Receivers
Abstract:
A design flow of multi-standard down-conversion CMOS mixers for three modern standards: Global System Mobile, Digital Enhanced Cordless Telephone and Universal Mobile Telecommunication Systems is presented. Three active mixer-s structures are studied. The first is based on the Gilbert cell which gives a tolerable noise figure and linearity with a low conversion gain. The second and third structures use the current bleeding and charge injection techniques in order to increase the conversion gain. An improvement of about 2 dB of the conversion gain is achieved without a considerable degradation of the other characteristics. The models used for noise figure, conversion gain and IIP3 used are studied. This study describes the nature of trade-offs inherent in such structures and gives insights that help in identifying which structure is better for given conditions.
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