The reliability of the power grid depends on the successful operation of thousands of protective relays. The failure of one relay to operate as intended may lead the entire power grid to blackout. In fact, major power system failures during transient disturbances may be caused by unnecessary protective relay tripping rather than by the failure of a relay to operate. Adequate relay testing provides a first defense against false trips of the relay and hence improves power grid stability and prevents catastrophic bulk power system failures. The goal of this research project is to design and enhance the relay tester using a technology such as Field Programmable Gate Array (FPGA) card NI 7851. A PC based tester framework has been developed using Simulink power system model for generating signals under different conditions (faults or transient disturbances) and LabVIEW for developing the graphical user interface and configuring the FPGA. Besides, the interface system has been developed for outputting and amplifying the signals without distortion. These signals should be like the generated ones by the real power system and large enough for testing the relay’s functionality. The signals generated that have been displayed on the scope are satisfactory. Furthermore, the proposed testing system can be used for improving the performance of protective relay.
In the inter-connected power systems, a phenomenon called inter-area oscillation may be caused by several defects. In this paper, a study of the Maghreb countries inter-area power networks oscillation has been investigated. The inter-area oscillation monitoring can be enhanced by integrating Phasor Measurement Unit (PMU) technology installed in different places. The data provided by PMU and recorded by PDC will be used for the monitoring, analysis, and control purposes. The proposed approach has been validated by simulation using MATLAB/Simulink.