Digital Predistorter with Pipelined Architecture Using CORDIC Processors
In a wireless communication system, a
predistorter(PD) is often employed to alleviate nonlinear distortions
due to operating a power amplifier near saturation, thereby improving
the system performance and reducing the interference to adjacent
channels. This paper presents a new adaptive polynomial digital
predistorter(DPD). The proposed DPD uses Coordinate Rotation
Digital Computing(CORDIC) processors and PD process by pipelined
architecture. It is simpler and faster than conventional adaptive
polynomial DPD. The performance of the proposed DPD is proved by
Dynamic Data Partition Algorithm for a Parallel H.264 Encoder
The H.264/AVC standard is a highly efficient video
codec providing high-quality videos at low bit-rates. As employing
advanced techniques, the computational complexity has been
increased. The complexity brings about the major problem in the
implementation of a real-time encoder and decoder. Parallelism is the
one of approaches which can be implemented by multi-core system.
We analyze macroblock-level parallelism which ensures the same bit
rate with high concurrency of processors. In order to reduce the
encoding time, dynamic data partition based on macroblock region is
proposed. The data partition has the advantages in load balancing and
data communication overhead. Using the data partition, the encoder
obtains more than 3.59x speed-up on a four-processor system. This
work can be applied to other multimedia processing applications.
H.264/AVC, video coding, thread-level parallelism,OpenMP, multimedia
Low Cost Chip Set Selection Algorithm for Multi-way Partitioning of Digital System
This paper considers the problem of finding low cost
chip set for a minimum cost partitioning of a large logic circuits. Chip
sets are selected from a given library. Each chip in the library has a
different price, area, and I/O pin. We propose a low cost chip set
selection algorithm. Inputs to the algorithm are a netlist and a chip
information in the library. Output is a list of chip sets satisfied with
area and maximum partitioning number and it is sorted by cost. The
algorithm finds the sorted list of chip sets from minimum cost to
maximum cost. We used MCNC benchmark circuits for experiments.
The experimental results show that all of chip sets found satisfy the
multiple partitioning constraints.
lowest cost chip set, MCNC benchmark, multi-way
An Embedded System Design for SRAM SEU Test
An embedded system for SEU(single event upset) test
needs to be designed to prevent system failure by high-energy particles
during measuring SEU. SEU is a phenomenon in which the data is changed temporary in semiconductor device caused by high-energy particles. In this paper, we present an embedded system for
SRAM(static random access memory) SEU test. SRAMs are on the DUT(device under test) and it is separated from control board which
manages the DUT and measures the occurrence of SEU. It needs to
have considerations for preventing system failure while managing the
DUT and making an accurate measurement of SEUs. We measure the occurrence of SEUs from five different SRAMs at three different
cyclotron beam energies 30, 35, and 40MeV. The number of SEUs of SRAMs ranges from 3.75 to 261.00 in average.
embedded system, single event upset, SRAM
Programming Aid Tool for Detecting Common Mistakes of Novice Programmers in OpenMP Code
OpenMP is an API for parallel programming model of shared memory multiprocessors. Novice OpenMP programmers often produce the code that compiler cannot find human errors. It was investigated how compiler coped with the common mistakes that can occur in OpenMP code. The latest version(4.4.3) of GCC is used for this research. It was found that GCC compiled the codes without any errors or warnings. In this paper the programming aid tool is presented for OpenMP programs. It can check 12 common mistakes that novice programmer can commit during the programming of OpenMP. It was demonstrated that the programming aid tool can detect the various common mistakes that GCC failed to detect.
Parallel programming, OpenMP, programming aid.
Performance Analysis of Adaptive LMS Filter through Regression Analysis using SystemC
The LMS adaptive filter has several parameters which can affect their performance. From among these parameters, most papers handle the step size parameter for controlling the performance. In this paper, we approach three parameters: step-size, filter tap-size and filter form. The regression analysis is used for defining the relation between parameters and performance of LMS adaptive filter with using the system level simulation results. The results present that all parameters have performance trends in each own particular form, which can be estimated from equations drawn by regression analysis.
System level model, adaptive LMS FIR filter, regression analysis, systemC.
SystemC Modeling of Adaptive Least Mean Square Filter
In this paper, we demonstrate the adaptive
least-mean-square (LMS) filter modeling using SystemC. SystemC is
a modeling language that allows designer to model both hardware and
software component and makes it possible to design from high level
system of abstraction to low level system of abstraction. We produced
five adaptive least-mean-square filter models that are classed as five
abstraction levels using SystemC proceeding from the abstract model
to the more concrete model.
Adaptive Filter, Least-Mean-Square Algorithm,SystemC, Transversal Fir Filter.
Implementation of a Reed-Solomon Code as an ECC in Yet Another Flash File System
Flash memory has become an important storage device
in many embedded systems because of its high performance, low
power consumption and shock resistance. Multi-level cell (MLC) is
developed as an effective solution for reducing the cost and increasing
the storage density in recent years. However, most of flash file system
cannot handle the error correction sufficiently. To correct more errors
for MLC, we implement Reed-Solomon (RS) code to YAFFS, what is
widely used for flash-based file system. RS code has longer computing
time but the correcting ability is much higher than that of Hamming
Reed-Solomon, NAND flash memory, YAFFS, ErrorCorrecting Code, Flash File System
UML Model for Double-Loop Control Self-Adaptive Braking System
In this paper, we present an activity diagram model for double-loop control self-adaptive braking system. Since activity diagram helps to improve visibility of self-adaption. We can easily find where improvement is needed on double-loop control. Double-loop control is adopted since the design conditions and actual conditions can be different. The system is reconfigured in runtime by using double-loop control. We simulated to verify and validate our model by using MATLAB. We compared single-loop control model with double-loop control model. Simulation results show that double-loop control provides more consistent brake power control than single-loop control.
Activity diagram, automotive, braking system, double-loop, Self-adaptive, UML, vehicle.
Exploring SSD Suitable Allocation Schemes Incompliance with Workload Patterns
In the Solid-State-Drive (SSD) performance, whether
the data has been well parallelized is an important factor. SSD
parallelization is affected by allocation scheme and it is directly
connected to SSD performance. There are dynamic allocation and
static allocation in representative allocation schemes. Dynamic
allocation is more adaptive in exploiting write operation parallelism,
while static allocation is better in read operation parallelism.
Therefore, it is hard to select the appropriate allocation scheme when
the workload is mixed read and write operations. We simulated
conditions on a few mixed data patterns and analyzed the results to
help the right choice for better performance. As the results, if data
arrival interval is long enough prior operations to be finished and
continuous read intensive data environment static allocation is more
suitable. Dynamic allocation performs the best on write performance
and random data patterns.
Dynamic allocation, NAND Flash based SSD, SSD
parallelism, static allocation.
Investigating Activity Recognition Using 9-Axis Sensors and Filters in Wearable Devices
In this paper, we analyze major components of activity recognition (AR) in wearable device with 9-axis sensors and sensor fusion filters. 9-axis sensors commonly include 3-axis accelerometer, 3-axis gyroscope and 3-axis magnetometer. We chose sensor fusion filters as Kalman filter and Direction Cosine Matrix (DCM) filter. We also construct sensor fusion data from each activity sensor data and perform classification by accuracy of AR using Naïve Bayes and SVM. According to the classification results, we observed that the DCM filter and the specific combination of the sensing axes are more effective for AR in wearable devices while classifying walking, running, ascending and descending.
Accelerometer, activity recognition, directional cosine matrix filter, gyroscope, Kalman filter, magnetometer.
Single Event Transient Tolerance Analysis in 8051 Microprocessor Using Scan Chain
As semi-conductor manufacturing technology evolves; the single event transient problem becomes more significant issue. Single event transient has a critical impact on both combinational and sequential logic circuits, so it is important to evaluate the soft error tolerance of the circuits at the design stage. In this paper, we present a soft error detecting simulation using scan chain. The simulation model generates a single event transient randomly in the circuit, and detects the soft error during the execution of the test patterns. We verified this model by inserting a scan chain in an 8051 microprocessor using 65 nm CMOS technology. While the test patterns generated by ATPG program are passing through the scan chain, we insert a single event transient and detect the number of soft errors per sub-module. The experiments show that the soft error rates per cell area of the SFR module is 277% larger than other modules.
Scan chain, single event transient, soft error, 8051 processor.
Effects of Incident Angle and Distance on Visible Light Communication
Visible Light Communication (VLC) provides wireless communication features in illumination systems. One of the key applications is to recognize the user location by indoor illuminators such as light emitting diodes. For localization of individual receivers in these systems, we usually assume that receivers and transmitters are placed in parallel. However, it is difficult to satisfy this assumption because the receivers move randomly in real case. It is necessary to analyze the case when transmitter is not placed perfectly parallel to receiver. It is also important to identify changes on optical gain by the tilted angles and distances of them against the illuminators. In this paper, we simulate optical gain for various cases where the tilt of the receiver and the distance change. Then, we identified changing patterns of optical gains according to tilted angles of a receiver and distance. These results can help many VLC applications understand the extent of the location errors with regard to optical gains of the receivers and identify the root cause.
Visible light communication, optical channel, indoor positioning, Lambertian radiation.
A Case Study of Limited Dynamic Voltage Frequency Scaling in Low-Power Processors
Power management techniques are necessary to save power in the microprocessor. By changing the frequency and/or operating voltage of processor, DVFS can control power consumption. In this paper, we perform a case study to find optimal power state transition for DVFS. We propose the equation to find the optimal ratio between executions of states while taking into account the deadline of processing time and the power state transition delay overhead. The experiment is performed on the Cortex-M4 processor, and average 6.5% power saving is observed when DVFS is applied under the deadline condition.
Deadline, Dynamic Voltage Frequency Scaling, Power State Transition.