Open Science Research Excellence

Manisha Pattanaik

Publications

2

Publications

2
2788
A ±0.5V BiCMOS Class-A Current Conveyor
Abstract:
In this paper, a new BiCMOS CCII and CCCII, capable of operate at ±0.5V and having wide dynamic range with achieved bandwidth of 480MHz and 430MHz respectively have been proposed. The structures have been found to be insensitive to the threshold voltage variations. The proposed circuits are suitable for implementation using 0.25μm BiCMOS technology. Pspice simulations confirm the performance of the proposed structures.
Keywords:
BiCMOS, Current conveyor, Compound current conveyor, Low supply voltage, Threshold voltage variation.
1
9997080
Leakage Reduction ONOFIC Approach for Deep Submicron VLSI Circuits Design
Abstract:

Minimizations of power dissipation, chip area with higher circuit performance are the necessary and key parameters in deep submicron regime. The leakage current increases sharply in deep submicron regime and directly affected the power dissipation of the logic circuits. In deep submicron region the power dissipation as well as high performance is the crucial concern since increasing importance of portable systems. Number of leakage reduction techniques employed to reduce the leakage current in deep submicron region but they have some trade-off to control the leakage current. ONOFIC approach gives an excellent agreement between power dissipation and propagation delay for designing the efficient CMOS logic circuits. In this article ONOFIC approach is compared with LECTOR technique and output results show that ONOFIC approach significantly reduces the power dissipation and enhance the speed of the logic circuits. The lower power delay product is the big outcome of this approach and makes it an influential leakage reduction technique.

Keywords:
Deep submicron, Leakage Current, LECTOR, ONOFIC, Power Delay Product