Open Science Research Excellence

Navab Singh

Publications

3

Publications

3
13780
Integration of Resistive Switching Memory Cell with Vertical Nanowire Transistor
Abstract:
We integrate TiN/Ni/HfO2/Si RRAM cell with a vertical gate-all-around (GAA) nanowire transistor to achieve compact 4F2 footprint in a 1T1R configuration. The tip of the Si nanowire (source of the transistor) serves as bottom electrode of the memory cell. Fabricated devices with nanowire diameter ~ 50nm demonstrate ultra-low current/power switching; unipolar switching with 10μA/30μW SET and 20μA/30μW RESET and bipolar switching with 20nA/85nW SET and 0.2nA/0.7nW RESET. Further, the switching current is found to scale with nanowire diameter making the architecture promising for future scaling.
Keywords:
RRAM, 1T1R, gate-all-around FET, nanowire FET, vertical MOSFETs
2
10002143
Preparation of Porous Metal Membrane by Thermal Annealing for Thin Film Encapsulation
Abstract:
This paper presents thermal annealing de-wetting technique for the preparation of porous metal membrane for Thin Film Encapsulation (TFE) application. Thermal annealing de-wetting experimental results reveal that pore size formation in porous metal membrane depend upon i.e. 1. The substrate at which metal is deposited, 2. Melting point of metal used for porous metal cap layer membrane formation, 3. Thickness of metal used for cap layer, 4. Temperature used for formation of porous metal membrane. In order to demonstrate this technique, Silver (Ag) was used as a metal for preparation of porous metal membrane on amorphous silicon (a-Si) and silicon oxide. The annealing of the silver thin film of various thicknesses was performed at different temperature. Pores in porous silver film were analyzed using Scanning Electron Microscope (SEM). In order to check the usefulness of porous metal film for TFE application, the porous silver film prepared on amorphous silicon (a- Si) and silicon oxide was released using XeF2 and VHF, respectively. Finally, guide line and structures are suggested to use this porous membrane for robust TFE application.
Keywords:
De-wetting, thermal annealing, metal, melting point, porous.
1
10002144
The Design, Development, and Optimization of a Capacitive Pressure Sensor Utilizing an Existing 9 DOF Platform
Abstract:
Nine Degrees of Freedom (9 DOF) systems are already in development in many areas. In this paper, an integrated pressure sensor is proposed that will make use of an already existing monolithic 9 DOF inertial MEMS platform. Capacitive pressure sensors can suffer from limited sensitivity for a given size of membrane. This novel pressure sensor design increases the sensitivity by over 5 times compared to a traditional array of square diaphragms while still fitting within a 2 mm x 2 mm chip and maintaining a fixed static capacitance. The improved design uses one large diaphragm supported by pillars with fixed electrodes placed above the areas of maximum deflection. The design optimization increases the sensitivity from 0.22 fF/kPa to 1.16 fF/kPa. Temperature sensitivity was also examined through simulation.
Keywords:
Capacitive pressure sensor, 9 DOF, 10 DOF, sensor, capacitive, inertial measurement unit, IMU, inertial navigation system, INS.