New Corneal Reflection Removal Method Used In Iris Recognition System
Images of human iris contain specular highlights due
to the reflective properties of the cornea. This corneal reflection
causes many errors not only in iris and pupil center estimation but
also to locate iris and pupil boundaries especially for methods that
use active contour. Each iris recognition system has four steps:
Segmentation, Normalization, Encoding and Matching. In order to
address the corneal reflection, a novel reflection removal method is
proposed in this paper. Comparative experiments of two existing
methods for reflection removal method are evaluated on CASIA iris
image databases V3. The experimental results reveal that the
proposed algorithm provides higher performance in reflection
iris, pupil, specular highlights, reflection removal
Multi Band Frequency Synthesizer Based on ISPD PLL with Adapted LC Tuned VCO
The 4G front-end transceiver needs a high
performance which can be obtained mainly with an optimal
architecture and a multi-band Local Oscillator. In this study, we
proposed and presented a new architecture of multi-band frequency
synthesizer based on an Inverse Sine Phase Detector Phase Locked
Loop (ISPD PLL) without any filters and any controlled gain block
and associated with adapted multi band LC tuned VCO using a
several numeric controlled capacitive branches but not binary
weighted. The proposed architecture, based on 0.35μm CMOS
process technology, supporting Multi-band GSM/DCS/DECT/
UMTS/WiMax application and gives a good performances: a phase
noise @1MHz -127dBc and a Factor Of Merit (FOM) @ 1MHz -
186dB and a wide band frequency range (from 0.83GHz to 3.5GHz),
that make the proposed architecture amenable for monolithic
integration and 4G multi-band application.
GSM/DCS/DECT/UMTS/WiMax, ISPD PLL, keep
and capture range, Multi-Band, Synthesizer, Wireless.
Efficient Hardware Architecture of the Direct 2- D Transform for the HEVC Standard
This paper presents the hardware design of a unified
architecture to compute the 4x4, 8x8 and 16x16 efficient twodimensional
(2-D) transform for the HEVC standard. This
architecture is based on fast integer transform algorithms. It is
designed only with adders and shifts in order to reduce the hardware
cost significantly. The goal is to ensure the maximum circuit reuse
during the computing while saving 40% for the number of operations.
The architecture is developed using FIFOs to compute the second
dimension. The proposed hardware was implemented in VHDL. The
VHDL RTL code works at 240 MHZ in an Altera Stratix III FPGA.
The number of cycles in this architecture varies from 33 in 4-point-
2D-DCT to 172 when the 16-point-2D-DCT is computed. Results
show frequency improvements reaching 96% when compared to an
architecture described as the direct transcription of the algorithm.
HEVC, Modified Integer Transform, FPGA.