Open Science Research Excellence

Wee Leong Son

Publications

2

Publications

2
5640
High-Resolution 12-Bit Segmented Capacitor DAC in Successive Approximation ADC
Abstract:
This paper study the segmented split capacitor Digital-to-Analog Converter (DAC) implemented in a differentialtype 12-bit Successive Approximation Analog-to-Digital Converter (SA-ADC). The series capacitance split array method employed as it reduced the total area of the capacitors required for high resolution DACs. A 12-bit regular binary array structure requires 2049 unit capacitors (Cs) while the split array needs 127 unit Cs. These results in the reduction of the total capacitance and power consumption of the series split array architectures as to regular binary-weighted structures. The paper will show the 12-bit DAC series split capacitor with 4-bit thermometer coded DAC architectures as well as the simulation and measured results.
Keywords:
Successive Approximation Register Analog-to- Digital Converter, SAR ADC, Low voltage ADC.
1
9999685
Pulse Generator with Constant Pulse Width
Abstract:

This paper is about method to produce a stable and accurate constant output pulse width regardless of the amplitude, period and pulse width variation of the input signal source. The pulse generated is usually being used in numerous applications as the reference input source to other circuits in the system. Therefore, it is crucial to produce a clean and constant pulse width to make sure the system is working accurately as expected.

Keywords:
Amplitude, Constant Pulse Width, Frequency Divider, Pulse Generator.