In this paper we ultra low-voltage and high speed CMOS domino logic. For supply voltages below 500mV the delay for a ultra low-voltage NAND2 gate is aproximately 10% of a complementary CMOS inverter. Furthermore, the delay variations due to mismatch is much less than for conventional CMOS. Differential domino gates for AND/NAND and OR/NOR operation are presented.
The problem discussed in this paper involves packing fresh fish fileet of the northern Cod into a standard square container. The fish is first cleaned and split and then collected on a belt ready to be stacked in a container. The aim of our work is to pack the fish into the container with constraints on the amount of overlap allowed for the fileets. The current focus is to design a packing cell that can be real-time and of practical use, while finding the optimal solution to the degree of overlap and minimise the unused space of the container.
In this paper we promote the Ultra Low Voltage (ULV) NAND gate to replace either partly or entirely the encryption block of a design to withstand power analysis attack.
In this paper we present a linear autozeroing ultra lowvoltage amplifier. The autozeroing performed by all ULV circuits is important to reduce the impact of noise and especially avoid power supply noise in mixed signal low-voltage CMOS circuits. The simulated data presented is relevant for a 90nm TSMC CMOS process.