|Commenced in January 1999||Frequency: Monthly||Edition: International||Paper Count: 2|
The dynamic variation in memory devices such as the Static Random Access Memory can give errors in read or write operations. In this paper, the effect of low-frequency and random telegraph noise on the dynamic variation of one SRAM cell is detailed. The effect on circuit noise, speed, and length of time of processing is examined, using the Supply Read Retention Voltage and the Read Static Noise Margin. New test run methods are also developed. The obtained results simulation shows the importance of noise caused by dynamic variation, and the impact of Random Telegraph noise on SRAM variability is examined by evaluating the statistical distributions of Random Telegraph noise amplitude in the pull-up, pull-down. The threshold voltage mismatch between neighboring cell transistors due to intrinsic fluctuations typically contributes to larger reductions in static noise margin. Also the contribution of each of the SRAM transistor to total dynamic variation has been identified.
The present paper provides a detailed analysis of prior methods and approaches for non-linear load identification in residential buildings. The main goal of this analysis is to decipher the distorted signals and to estimate the harmonics influence on power systems. We have performed an analytical study of non-linear loads behavior in the residential environment. Simulations have been performed in order to evaluate the distorted rate of the current and follow his behavior. To complete this work, an instrumental platform has been realized to carry out practical tests on single-phase non-linear loads which illustrate the current consumption of some domestic appliances supplied with single-phase sinusoidal voltage. These non-linear loads have been processed and tracked in order to limit their influence on the power grid and to reduce the Joule effect losses. As a result, the study has allowed to identify responsible circuits of harmonic pollution.