Power plane noise is the most significant source of signal integrity (SI) issues in a high-speed digital design. In this paper, power integrity (PI) analysis of multiple power planes in a power delivery system of a 12-layer high-speed FPGA board is presented. All 10 power planes of HSD board are analyzed separately by using 3D Electromagnetic based PI solver, then the transient simulation is performed on combined PI data of all planes along with voltage regulator modules (VRMs) and 70 current drawing chips to get the board level power noise coupling on different high-speed signals. De-coupling capacitors are placed between power planes and ground to reduce power noise coupling with signals.
A compact planar monopole antenna with dual-band operation suitable for wireless local area network (WLAN) application is presented in this paper. The antenna occupies an overall area of 18 ×12 mm2. The antenna is fed by a coplanar waveguide (CPW) transmission line and it combines two folded strips, which radiates at 2.4 and 5.2 GHz. In the proposed antenna, by optimally selecting the antenna dimensions, dual-band resonant modes with a much wider impedance matching at the higher band can be produced. Prototypes of the obtained optimized design have been simulated using EM solver. The simulated results explore good dual-band operation with -10 dB impedance bandwidths of 50 MHz and 2400 MHz at bands of 2.4 and 5.2 GHz, respectively, which cover the 2.4/5.2/5.8 GHz WLAN operating bands. Good antenna performances such as radiation patterns and antenna gains over the operating bands have also been observed. The antenna with a compact size of 18×12×1.6 mm3 is designed on an FR4 substrate with a dielectric constant of 4.4.